VSC8022FI 参数 Datasheet PDF下载

VSC8021/VSC8022

Data Sheet

G52028-0, Rev 4.1

05/25/01

VSC8022 AC Characteristics

(Over recommended operating conditions)

t

C

CLKI

(1)

(CLKIN)

t

OOFNPW

t

OOFN

SONET STS-3 Framing Sequence

DATA

DATA

DATA

DATA

DATA

High speed differential clock input

OOFN

Frame recovery clock input

©

VITESSE

SEMICONDUCTOR CORPORATION

• 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

DI (DIN)

High speed serial data inputs

A1

A1

A1

A2

A2

A2

Figure 4: VSC8022 Demultiplexer Waveforms

t

D

BYCKO (BYCKON)

Byte clock output

BYCKO

Resynch

VITESSE

SEMICONDUCTOR CORPORATION

t

BD

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Data

Data

Data

Data

Data

Data

Data

Data

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Data

Data

Data

Data

Data

Data

Data

Data

D1 (D1N)

D2 (D2N)

D3 (D3N)

D4 (D4N)

D5 (D5N)

D6 (D6N)

D7 (D7N)

D8 (D8N)

Parallel Data•

(2)

Output Summary

FP

Frame detection confirm output

NOTES:

1) Negative edge is active edge.

A1

A1

t

DFP

A2

A2

A2

t

PFP

Data

Data

Data

Data

2.5Gb/s SONET-Compatible

8-Bit MUX/DEMUX Chipset

2) The parallel data outputs only begin showing valid data after the last A2 of the SONET framing sequence. The example

waveforms shown above use an STS-3 framing sequence for convenience, thus valid data is output after the third

A2 in the sequence.

= Don’t care.

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