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VSC7984YF 参数 Datasheet PDF下载

VSC7984YF图片预览
型号: VSC7984YF
PDF下载: 下载PDF文件 查看货源
内容描述: [Display Driver, PQCC24,]
分类和应用:
文件页数/大小: 16 页 / 268 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VSC7984  
Datasheet  
AC Characteristics  
Specifications are guaranteed over the recommended operating conditions listed in Table 3, page 10. Data input  
31  
pattern at PRBS 2 –1 and 11.3 Gbps, unless otherwise noted.  
Table 2. AC Characteristics  
Symbol  
fDATA  
fCLK  
Parameter  
Data rate  
Clock rate  
MinImum  
Typical  
11.3  
Maximum  
12.5  
Unit  
Condition  
Gbps NRZ.  
GHz  
1
11.3  
12.5  
VIN  
Single-ended data input voltage  
amplitude  
0.3  
1.0  
V
AC-coupled, measured peak-  
to-peak. See Figure 9.  
Differential data input voltage  
amplitude  
0.3  
0.4  
0.4  
1.0  
1.0  
V
AC-coupled, measured peak-  
to-peak (150 mV per side).  
See Figure 9.  
VCLK  
Single-ended clock input voltage  
amplitude  
V
V
AC-coupled, measured peak-  
to-peak.  
See Figure 9.  
Differential clock input voltage  
amplitude  
1.0  
AC-coupled, measured peak-  
to-peak (200 mV per side).  
See Figure 9.  
VOC  
Output compliance voltage  
VCC – 3.5  
V
V
RL = 50 Ω, VCC – VEE 4.9 V  
VOM 2.7 V. See Figure 3.  
VCC – 3.3  
RL = 50 Ω, VCC – VEE 4.75 V  
VOM 2.7 V. See Figure 3.  
VOM  
Output modulation voltage  
Disabled output current  
1.4  
2.7  
5
V
mA  
ps  
%
RL = 50 Ω.  
IOM_DIS  
tR, tF  
ENABLE = LOW.  
Output rise time and fall time  
Data eye crossing point range  
25  
35  
85  
7
20% to 80%, RL = 50 Ω.  
See Figure 6 and Figure 7.  
DCC  
25  
–7  
DCCSTAB Data eye crossing point stability  
%
VPW  
Pulse width control input(1)  
VEE + 0.5  
VEE + 2.5  
V
For 50% crossing point at  
OUT, set VPW = VEE + 1.1 V.  
See Figure 6.  
–OVS  
+OVS  
Output undershoot /overshoot  
Clock select  
–12  
10  
%
VOM > 1.4 V.  
CSEL  
Floating  
V
Unclocked mode.  
Clocked mode.  
VEE  
0
VEE + 0.3  
V
tS  
Setup time  
Hold time  
–11  
25  
ps  
ps  
ps  
ps  
ps  
ps  
dB  
dB  
dB  
dB  
See Figure 8.  
tH  
30  
See Figure 8.  
JTOT_rms  
Total jitter, rms  
2.1  
2.2  
12  
4
6
Clocked mode.  
Unclocked mode.  
Clocked mode.  
JTOT_p-p  
Total jitter, peak-to-peak  
Clock input return loss  
Data input return loss  
Data output return loss  
16  
18  
14  
Unclocked mode.  
1 GHz to 10 GHz.  
10 GHz to 15 GHz.  
50 MHz to 10 GHz.  
10 GHz to 15 GHz.  
50 MHz to 7.5 GHz.  
7.5 GHz to 10 GHz.  
S11  
–11  
–9  
S11  
–11  
–10  
–11  
–9  
S22  
1. The VSC7984 is capable of moving the data eye crossing point to the very top and bottom of the eye diagram.  
8 of 16  
VMDS-10029 Revision 4.1  
January 19, 2007  
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