VITESSE
VITESSE
SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
Gigabit Interconnect Chip
VSC7212
Elastic Buffer and Channel De-Skewing
An elastic buffer is included in the receiver. Decoded data and status information is written into these
buffers with the recovered clock, and is read with the selected word clock (either the recovered clock or
REFCLK). In addition to allowing decoded data to easily cross from a receiver’s recovered clock domain to its
output clock domain, the elastic buffer facilitates chip-to-chip alignment (the reconstruction of a multi-byte
word as presented to the transmitting devices), and facilitates rate matching via IDLE character insertion/
deletion when the receiver’s recovered clock is not frequency-locked to its selected word clock.
There are three conditions under which a receiver’s elasticity buffer is recentered. The RESETN input,
when asserted LOW, recenters the read/write pointers in the elasticity buffer. Whenever a “Comma” character is
received which changes the receive character’s framing boundary, the elasticity buffer is recentered. Lastly, it is
also recentered whenever the receiver detects the synchronization point in the Word Sync Sequence. All three of
these events are associated with chip initialization or link initialization and would not occur during normal data
transfer. Note that recentering can result in the loss or duplication of decoded character data and status
information.
When a condition changes transmit timing (e.g., phase shifts in TBC) or shifts phase/alignment into the
receiver, the user should resend a Word Sync Event or assert RESETN in order to recenter the elasticity buffer.
Otherwise, data corruption could occur. It is unsafe to assume that after a change in transmit timing that
“Comma” characters will be misaligned and will cause recentering
The VSC7212 presents recovered data on R(7:0) and status on IDLE, KCH and ERR. These outputs are
timed either to the receiver’s recovered clock (RCLK/RCLKN) or to REFCLK. The output timing reference is
selected by RMODE(1:0) (see Table 5). TBERR, PSDET and RSDET are also synchronized to the selected
word clock. There are two choices for REFCLK-based timing, which differ in the positioning of the data valid
window associated with the output signals timed to REFCLK. When RMODE(1:0)=00 REFCLK is
approximately centered in the output data valid window as in the VSC7211 or VSC7214. When
RMODE(1:0)=01 REFCLK slightly leads the data valid window so that output data appears to have a more
typical “Clock-to-Q” timing relationship to REFCLK.
Table 5: Receive Interface Output Timing Mode
RMODE(1:0)
Output Timing Reference
0 0
0 1
REFCLK (Centered)
REFCLK (Leading)
RCLK/RCLKN
1 X
The term “word clock” will be used for whichever clock, REFCLK or RCLK/RCLKN, is selected as the
output timing reference. If RMODE(1) is HIGH, the receiver’s RCLK/RCLKN outputs are complementary
outputs at 1/10th or 1/20th the baud rate of the incoming data depending upon DUAL. If RMODE(1) is LOW,
then the RCLK/RCLKN outputs are held HIGH/LOW and the data bus and status outputs are timed to
REFCLK. If DUAL is HIGH, all data at the receiver’s output port is synchronously clocked out on both positive
and negative edges of the selected word clock at 1/20th the baud rate. If DUAL is LOW, the data is clocked out
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
G52268-0, Rev 3.3
04/10/01
Page 9
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