ESE
VITESSE
SEMICONDUCTOR
CORPORATION
SEMICONDUCTOR
CORPORATION
Preliminary Data Sheet
Gigabit Interconnect Chip
VSC7212
Word Sync Generation
The VSC7212 can perform chip-to-chip alignment (also referred to as “word alignment” or “word sync”),
meaning that the receive data output streams from multiple chips are aligned such that the same n-byte word
presented to the n transmit channels for serialization will be transferred on the receive channel parallel outputs.
The Word Sync Sequence provides a unique synchronization point in the serial data stream that is used to align
the receive channels. This sequence consists of 16 consecutive K28.5 IDLE characters with disparity reversals
on the second and fourth characters. The Word Sync Sequence is sent either as “I+ I+ I- I- I+ I- I+ I- I+ I- I+ I-
I+ I- I+ I-” or as “I- I- I+ I+ I- I+ I- I+ I- I+ I- I+ I- I+ I- I+”, depending on the transmitter’s running disparity at
the time the first IDLE character is serialized.
Transmission of the Word Sync Sequence is initiated when the WSEN input is asserted HIGH for one
character time (see Figure 5). When WSEN is HIGH, the C/D and T(7:0) inputs are ignored. The WSEN, C/D
and T(7:0) inputs are also ignored for the subsequent 15 character times. In Figure 5, the Word Sync Sequence
is initiated in cycle W1 and transmitted through cycle W16. Normal data transmission (or the transmission of
another Word Sync Sequence) resumes in cycle D3. This figure is drawn assuming that input timing is
referenced to REFCLK (e.g. TMODE(2:0)=000) with the DUAL input LOW. As long as WSEN remains
asserted, another Word Sync Sequence will be generated.
Figure 5: Word Sync Sequence Generation
D1
D2
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
D3
D4
REFCLK
WSEN
C/D
T(7:0)
TX+/-
0x01
0x02
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
0x03
0x04
D1.0+
D2.0+ K28.5+ K28.5+ K28.5- K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ K28.5- D3.0+
D4.0-
Serializer
The 10-bit output from the encoder (or from the skew buffer if ENDEC is LOW) is fed into a multiplexer
which serializes the parallel data using the synthesized transmit clock. The least significant bit of the 10B data is
transmitted first. The VSC7212 has both primary and redundant serial output ports, PTX and RTX, respectively,
which consist of differential PECL output buffers operating at either 10 or 20 times the REFCLK rate. The
primary and redundant transmitter outputs are separately controllable. The primary PECL outputs PTX are
enabled when the PTXEN input is HIGH, and the redundant PECL outputs RTX are enabled when the RTXEN
input is HIGH. When a PECL output is disabled, the associated output buffers do not consume power and the
attached pins are un-driven.
Page 6
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VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52268-0, Rev 3.3
04/10/01
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