ESE
VITESSE
SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
Gigabit Interconnect Chip
VSC7212
of the VSC7212 only on the rising edge of the selected word clock at 1/10th the baud rate. Timing waveforms
for the output data and status are shown in Figure 6, Figure 7 and Figure 8.
Figure 6: Receive Timing, RMODE(1:0) = 00
REFCLK
(DUAL = 0)
REFCLK
(DUAL = 1)
R(7:0)
IDLE
KCH
ERR
Valid
Valid
Valid
Figure 7: Receive Timing, RMODE(1:0) = 01
REFCLK
(DUAL = 0)
REFCLK
(DUAL = 1)
R(7:0)
IDLE
KCH
ERR
Valid
Valid
Valid
Figure 8: Receive Timing, RMODE(1:0) = 1X
RCLK
(DUAL = 0)
RCLK
(DUAL = 1)
R(7:0)
IDLE
KCH
ERR
Valid
Valid
Valid
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Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 10
G52268-0, Rev 3.3
04/10/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
