VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7125
Figure 8: Transmitter Jitter Measurement Method
1.0625 Gbits/sec Fibre
Channel Transceiver
BERT
Pattern
Generator
1.0625 GHz Clock
DATA
DATA
106.25MHz
Trigger
Digitizing
Scope
VSC7125
TX
RJ
DJ
-K28.7 -K28.7
0011111000 0011111000
-K28.5 +K28.5
0011111010 1100000101
REFCLK TX+
TX-
T0:9
1.0625 Gb/s
Single-Ended Measurement
Random jitter (RJ) measurements performed according to Fibre Channel 4.3 Annex A, Test Methods, Section A.4.4. Measure
standard deviation of all 50% crossing points. Peak to peak RJ is + 7 sigma of distribution.
Deterministic jitter (DJ) measurements performed according to Fibre Channel 4.3 Annex A, Test Methods, Section A.4.3.
Measure time of all the 50% points of all ten transitions. DJ is the range of the timing variations.
Figure 9: Input Structures
V
DD
+3.3 V
V
DD
+3.3 V
INPUT
INPUT
Current
Limit
R
INPUT
R
GND
GND
All Resistors
3.3K
REFCLK and TTL Inputs
High Speed Differential Input
(RX+/RX-)
A
B
G52121-0, Rev. 4.1
4/23/98
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 9
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