VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
1.0625 Gbits/sec Fibre
Channel Transceiver
VSC7125
Table 2: Receive AC Characteristics
Parameters
Description
Min.
Max.
Units
Conditions
Data or COM_DET Valid
prior to RCLK/RCLKN
rise
Measured between the
1.4V point of RCLK or
RCLKN and a valid level
of R0:9. All outputs
4.0
—
ns.
T
T
1
2
Data or COM_DET Valid
after RCLK or RCLKN
rise
3.0
—
ns.
ps.
driving 10pF load.
Deviation of RCLK
rising edge to RCLKN
rising edge delay from
nominal.
Nominal delay is 10 bit
times. Tested on sample
basis
-500
500
T
T
3
4
f baud
delay= ------------- ± T 3
10
Deviation of RCLK,
RCLKN frequency from
nominal.
Whether or not locked to
serial data
-1.0
1.0
%
f REFCLK
f RCLK= ---------------------- ± T 4
2
R0:9, COM_DET, RCLK,
RCLKN rise and fall time
Between V
and
il(max)
—
15bc + 2ns
—
2.4
34bc + 2ns
2.4
ns.
T , T
R
F
V
, into 10 pf. load.
ih(min)
bc = Bit clock
ns = Nano second
R
Latency from RX to R0:9
lat
Data acquisition lock time
@ 1.0625Gb/s
8B/10B IDLE pattern.
Tested on a sample basis
µs.
T
LOCK
Receive Data Jitter Power
-12
dBc, RMS for l0 Bit
1
------------------------------
2 × BitTime
Receive Data
Jitter
—
40
ps.
Error Ratio Tested on a
sample basis
PhaseNoise
∫
100KHz
Note: Probability of recovery for data acquisition is 95% per section 5.3 of the FC-PH rev. 4.3.
Page 6
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52121-0, Rev. 4.1
4/23/98
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
