VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
1.0625 Gbits/sec Fibre
Channel Transceiver
VSC7125
Table 4: Pin Identification
Pin #
Name
Description
INPUT - TTL
19
EWRAP
LOW for Normal Operation. When HIGH, an internal loopback path from the
transmitter to the receiver is enabled and the TX outputs are held HIGH.
INPUTS - Differential PECL (AC Coupling recommended)
54, 52
31, 30
24
RX+, RX-
The serial receive data inputs selected when EWRAP is LOW. Internally biased tot
VDD/2, with 3.3KΩ resistors from each input pin to VDD and GND.
OUTPUT - Complementary TTL
Recovered clocks derived from one twentieth of the RX+/- data stream. Each rising
transition of RCLK or RCLKN corresponds to a new word on R0:9.
RCLK,
RCLKN
INPUT - TTL
EN_CDET
COMDET
Enables COMDET and word resynchronization when HIGH. When LOW, keeps
current word alignment and disables COMDET.
OUTPUT - TTL
This output goes HIGH for half of an RCLK period to indicate that R0:9 contains a
Comma Character (‘0011111XXX’). COMDET will go HIGH only during a cycle
when RCLKN is rising. COMDET is enabled by EN_CDET being HIGH.
47
TEST1
TEST2
TEST3
INPUT
18,20,23
26
These signals are used for factory test. For normal operation, tie to VDD.
OUTPUT
TEST_4
This signal is used for factory test. For normal operation, leave open.
57
58
VDDANA
VSSANA
Analog Power Supply
Analog Ground
5, 10, 28,
50, 55, 59
VDDD
VSSD
Digital Logic Power Supply
Digital Logic Ground
1, 14, 15,
21, 25,
51, 56
29, 37, 42
32, 33, 46
53, 60, 63
VDDT
VSST
VDDP
TTL Output Power Supply
TTL Output Ground
PECL I/O Power Supply
16,17,27,
48,49,64
N/C
No Connection. These pins are not internally connected.
Page 12
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52121-0, Rev. 4.1
4/23/98
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
