VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7125
Figure 5: Receive Timing Waveforms
T
4
T
3
1.0625 Gbits/sec Fibre
Channel Transceiver
RCLK
RCLKN
T
1
T
2
Data Valid
R0:9
Data Valid
Data Valid
Figure 6: REFCLK Timing Waveforms
T
L
REFCLK
T
H
V
ih(min)
V
il(max)
Table 3: Reference Clock Requirements
Parameters
Description
Min
Max
Unit
s
Conditions
Range over which both transmit and
receive reference clocks on any link
may be centered
Maximum frequency offset between
transmit and receive reference clocks
on one link
Measured at 1.5V
Between V
il(max)
and V
ih(min)
dbc, RMS for FC compliant output
data jitter
FR
Frequency Range
100
110
MHz
FO
DC
T
RCR
,T
RCF
REFCLK
Jitter
Frequency Offset
REFCLK duty cycle
REFCLK rise and fall time
REFCLK Jitter Power
5
MHz
-200
200
ppm.
30
—
70
2.0
%
ns.
∫
100Hz
PhaseNoise
—
2
ps.
REFCLK Jitter Power
REFCLK
Jitter
5MHz
∫
100Hz
PhaseNoise
—
40
ps.
dbc, RMS for 10
-12
Bit Error Ratio
with zero length external path. Tested
on a sample basis
G52121-0, Rev. 4.1
4/23/98
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 7
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