VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
1.0625 Gbits/sec Fibre
Channel Transceiver
VSC7125
Package Pin Descriptions
Figure 10: Pin Diagram
63
61
59
57
55
53
51
49
47
N/C
1
VSSD
COMDET
VSST
T0
T1
3
R0
T2
VDDD
45
43
41
39
37
35
33
5
R1
R2
T3
T4
7
VDDT
R3
R4
T5
T6
9
VDDD
R5
R6
11
13
15
T7
T8
T9
VDDT
R7
R8
VSSD
VSSD
N/C
R9
VSST
17
19
21
23
25
27
29
31
(Top View)
Table 4: Pin Identification
Pin #
Name
Description
INPUTS - TTL
2-4, 6-9,
11-13
T0:9
10-bit transmit character. Parallel data on this bus is clocked in on the rising edge of
REFCLK. The data bit corresponding to T0 is transmitted first.
INPUT - TTL
22
REFCLK
TX+, TX-
R0:9
This rising edge of this clock latches T0:9 into the input register. It also provides the
reference clock, at one tenth the baud rate to the PLL.
OUTPUTS - Differential PECL (AC Coupling recommended)
These pins output the serialized transmit data when EWRAP is LOW. When EWRAP
is HIGH, TX+ is HIGH and TX- is LOW.
62, 61
OUTPUTS - TTL
45-43, 41-
38, 36-34
10-bit received character. Parallel data on this bus is clocked out on the rising edges
of RCLK and RCLKN. R0 is the first bit received on RX+/RX-.
G52121-0, Rev. 4.1
4/23/98
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 11
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