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Subject to Change
VSC7111 Datasheet
Contents
Contents
Revision History..........................................................................................8
1
2
Product Overview...............................................................................9
Functional Descriptions....................................................................11
2.1 Reset and Initialization........................................................................................ 11
2.2 Page-Based Programming.................................................................................... 12
2.3 Static (Pin-Strap) Configuration............................................................................ 12
2.4 Two-Wire Serial Interface, Slave Mode .................................................................. 15
2.5 Two-Wire Serial Interface, Master Mode................................................................. 16
2.6 Four-Wire Serial Interface ................................................................................... 17
2.7 Power-Saving Green Mode................................................................................... 17
2.8 Input Signal Equalization..................................................................................... 17
2.9 Input Power and Termination Impedance............................................................... 19
2.10 Input LOS ......................................................................................................... 19
2.11 Output Pre-Emphasis.......................................................................................... 20
2.12 Output Power Level and Slew Rate........................................................................ 21
2.13 Output Signal Suppression and PCIe Electrical Idle ................................................. 22
2.14 PCI-Express Receive Detect ................................................................................. 22
3
Registers..........................................................................................25
3.1 Individual Register Map....................................................................................... 25
3.2 Global Programming........................................................................................... 26
3.3 Individual Registers............................................................................................ 27
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
Reserved............................................................................................... 28
Input Gain 1 .......................................................................................... 28
Input Gain 2 .......................................................................................... 28
Input State............................................................................................ 29
Input LOS.............................................................................................. 29
Input AEQ Control................................................................................... 30
Input ISE 1 Long .................................................................................... 30
Input ISE 1 Short ................................................................................... 31
Input ISE 2 Long .................................................................................... 31
3.3.10 Input ISE 2 Short ................................................................................... 31
3.3.11 Output PE 1 ........................................................................................... 31
3.3.12 Output PE 2 ........................................................................................... 32
3.3.13 Output Level.......................................................................................... 32
3.3.14 Output Mode.......................................................................................... 33
3.3.15 PCIe Control .......................................................................................... 34
3.3.16 Channel Status....................................................................................... 34
3.4 Global Registers................................................................................................. 34
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
Global MUX Select .................................................................................. 35
Global Input Gain 1................................................................................. 35
Global Input Gain 2................................................................................. 35
Global Input State .................................................................................. 36
Global Input LOS .................................................................................... 36
Global Output PE 1 ................................................................................. 37
Global Output PE 2 ................................................................................. 37
Global Output Level ................................................................................ 37
Global Output Mode ................................................................................ 38
3.4.10 Global Input ISE 1 Long........................................................................... 39
Revision 2.0
September 2010
Confidential
Page 3
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
