VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC6250
AC Timing Characteristics
Table 2: AC Timing Characteristics
Parameter
t
PDR(MIN),
t
PDF(MIN)
t
PDR(MAX),
t
PDF(MAX)
t
PD(SPAN)
t
RES
DNL
t
PWI
t
PWO
FRCK
DTDD
DTDT
PSRR
t
R
/t
F
t
REFIRE
J
O
1Gb/s 16-Channel
Drive-Side Deskew IC
Description
Propagation Delay, Minimum Delay
Propagation Delay, Maximum Delay
Propagation Delay, Span
Delay Element Resolution
Delay Differential Nonlinearity
Input Pulse Width
Output Pulse Width
Reference Clock Frequency
Variation in Delay vs. Duty Cycle
Variation in Delay vs Temperature
Power Supply Rejection Ratio
(1)
Output Rise Fall Times (20% to 80%)
Adjacent Edge Spacing
Output Jitter
Min
4.1
9.9
5.8
—
-2
0.75
0.5
-50
—
—
—
2
—
Typ
5
11.6
—
8
—
—
—
250
—
2
—
300
—
3
Max
6.5
13.5
7
20
+2
—
—
—
+50
—
230
—
—
—
Units
ns
ns
ns
ps
LSB
ns
ns
MHz
ps
ps/C°
ps/100mV
ps
ns
ps rms
NOTE: (1) Change in range of maximum delay.
.
Figure 7: AC Timing Diagram
DINx
t
PDF(MAX)
t
PDF(MIN)
t
PDR(MAX)
t
PDR(MIN)
DOUTx
t
PDR(SPAN)
t
PWO
t
PDF(SPAN)
G52197-0, Rev. 4.0
8/19/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 7
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
