VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC6250
1Gb/s 16-Channel
Drive-Side Deskew IC
The 32 delays (rising and falling edges for 16 channels) in the VSC6250 are programmed using a parallel
interface. Verniers are selected by a 5-bit address word and controlled by two function enable bits. Each vernier
requires 11 bits to set the delay value.
Power dissipation of the VSC6250 is less than 5W from a single -2V supply.
Table 1: Operational Mode Truth Table
Mode #
1
2
Mode Name
Cal Mode
User Mode
CALENN
0
1
Mode Description
Sets timing delays with each vernier selected with ADR [3:0] Serial Data
Input.
Generates timing delays as set by data in Cal Mode.
Figure 4: CAL Mode Timing Diagram
ADR[4:0]
CALENN
D[10:0]
MSB
LSB
Don’t Care
10
9
Load Calibration Register
Data Latch Transparent
Latch Data into Data Latch
Measure Delay
1 CAL Cycle
G52197-0, Rev. 4.0
8/19/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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