VSC6134
Datasheet
Table 84. Drop DW Overhead Processor/FEC Performance Monitor Registers
Address
0x700
0x701
0x702
0x703
0x704
0x705
0x706
0x707
0x708
0x709
0x70A
Register Name
Reference
Drop Decoder Bit Error Interrupt Mask Register
Drop Decoder Bit Error Status Register
DW Overhead Monitor Interrupt Mask Register 0
DW Overhead Monitor Status Register 0
DW Overhead Monitor Interrupt Mask Register 1
DW Overhead Monitor Status Register 1
DW Section Monitor Interrupt Mask Register
DW Section Monitor Status Register
See Section 3.8.1, page 280.
See Section 3.8.2, page 280.
See Section 3.8.5, page 282.
See Section 3.8.6, page 282.
See Section 3.8.7, page 284.
See Section 3.8.8, page 284.
See Section 3.8.9, page 286.
See Section 3.8.10, page 286.
See Section 3.8.11, page 288.
See Section 3.8.12, page 289.
See Section 3.8.13, page 290.
DW TCM Monitor Interrupt Mask Registera
DW Tandem Connection Monitor Status Register
DW Tandem Connection Monitor and Path Monitor Interrupt
Mask Register
0x70B
DW Tandem Connection Monitor and Path Monitor Status
Register
See Section 3.8.14, page 291.
0x70C
0x70D
0x70E
0x70F
0x710
0x711
0x712
0x713
0x714
0x715
0x716
0x717
0x718
0x719
0x71A
0x71B
0x71C
0x71D
DW Path Monitor Interrupt Mask Register
See Section 3.8.15, page 292.
See Section 3.8.16, page 293.
See Section 3.8.17, page 294.
See Section 3.8.18, page 294.
See Section 3.8.19, page 295.
See Section 3.8.20, page 295.
See Section 3.8.21, page 295.
See Section 3.8.22, page 296.
See Section 3.8.23, page 296.
See Section 3.8.24, page 296.
See Section 3.8.25, page 297.
See Section 3.8.26, page 297.
See Section 3.8.27, page 297.
See Section 3.8.28, page 298.
See Section 3.8.29, page 298.
See Section 3.8.30, page 298.
See Section 3.8.31, page 299.
See Section 3.8.32, page 299.
DW Path Monitor Status Register
DW Overhead Configuration Register 0
DW Overhead Configuration Register 1
Standard FEC Uncorrectable Code Word Count (LSW)
Standard FEC Uncorrectable Code Word Count (MSW)
Standard FEC Opposite Surround Bit Error Count (LSW)
Standard FEC Opposite Surround Bit Error Count (MSW)
Standard FEC Same Surrounds Bit Error Count (LSW)
Standard FEC Same Surrounds Bit Error Count (MSW)
Standard FEC Corrected Bit Error Count (LSW)
Standard FEC Corrected Bit Error Count (MSW)
Standard FEC Early Transition Bit Error Count (LSW)
StandardFEC Early Transition Bit Error Count (MSW)
Standard FEC Late Transition Bit Error Count (LSW)
Standard FEC Late Transition Bit Error Count (MSW)
Standard FEC Corrected Symbol Error Count (LSW)
Standard FEC Corrected Symbol Error Count (MSW)
211 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
