VSC6134
Datasheet
Table 84. Drop DW Overhead Processor/FEC Performance Monitor Registers (continued)
Address
0x73D
0x73E
0x73F
0x740
0x741
0x742
Register Name
Reference
Path Monitor BIP-8 Block Error Count Register (LSW)
Path Monitor BEI Count Register (MSW)
Path Monitor BEI Count Register (LSW)
Enhanced FEC Total Corrected Bit Error Count (LSW)
Enhanced FEC Total Corrected Bit Error Count (MSW)
See Section 3.8.61, page 312.
See Section 3.8.62, page 312.
See Section 3.8.63, page 313.
See Section 3.8.64, page 313.
See Section 3.8.65, page 313.
See Section 3.8.66, page 313.
Receive FEC Extended FEC 1 Uncorrectable Code Words
(LSW)
0x743
0x744
0x745
0x746
0x747
Receive FEC Extended FEC 1 Uncorrectable Code Words
(MSW)
See Section 3.8.67, page 314.
See Section 3.8.68, page 314.
See Section 3.8.69, page 314.
See Section 3.8.70, page 314.
See Section 3.8.71, page 315.
Receive FEC Extended FEC 2 Uncorrectable Code Words
(LSW)
Receive FEC Extended FEC 2 Uncorrectable Code Words
(MSW)
Receive FEC Extended FEC 3 Uncorrectable Code Words
(LSW)
Receive FEC Extended FEC 3 Uncorrectable Code Words
(MSW)
0x748
0x749
0x74A
0x74B
0x74C
0x74D
0x74E
0x74F
0x750
0x751
0x760
0x761
0x762
0x763
0x764
0x765
0x766
0x767
Enhanced FEC 4 Uncorrectable Code Word Count (LSW)
Enhanced FEC 4 Uncorrectable Code Word Count (MSW)
Receive FEC Extended FEC 1 Corrected Bit Errors (LSW)
Receive FEC Extended FEC 1 Corrected Bit Errors (MSW)
Receive FEC Extended FEC 2 Corrected Bit Errors (LSW)
Receive FEC Extended FEC 2 Corrected Bit Errors (MSW)
Receive FEC Extended FEC 3 Corrected Bit Errors (LSW)
Receive FEC Extended FEC 3 Corrected Bit Errors (MSW)
Receive FEC Extended FEC 4 Corrected Bit Errors (LSW)
Receive FEC Extended FEC 4 Corrected Bit Errors (MSW)
Standard FEC Corrected One Bit Error Count (LSW)
Standard FEC Corrected One Bit Error Count (MSW)
Standard FEC Corrected Zero Bit Error Count (LSW)
Standard FEC Corrected Zero Bit Error Count (MSW)
Enhanced FEC Corrected One Bit Error Count (LSW)
Enhanced FEC Corrected One Bit Error Count (MSW)
Enhanced FEC Corrected Zero Bit Error Count (LSW)
Enhanced FEC Corrected Zero Bit Error Count (MSW)
See Section 3.8.72, page 315.
See Section 3.8.73, page 315.
See Section 3.8.74, page 315.
See Section 3.8.75, page 316.
See Section 3.8.76, page 316.
See Section 3.8.77, page 316.
See Section 3.8.78, page 316.
See Section 3.8.79, page 317.
See Section 3.8.80, page 317.
See Section 3.8.81, page 317.
See Section 3.8.82, page 317.
See Section 3.8.83, page 318.
See Section 3.8.84, page 318.
See Section 3.8.85, page 318.
See Section 3.8.86, page 319.
See Section 3.8.87, page 319.
See Section 3.8.88, page 319.
See Section 3.8.89, page 319.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
