VSC6134
Datasheet
Notes:
●
Address is latched on the rising of the clock when TSN is asserted. This also indicates the start of a
bus cycle.
●
●
Data is latched one clock cycle after the beginning of a bus cycle is detected.
TAN is asserted only for one clock cycle.
2.16.4
Intel Processors
The Microprocessor interface unit of the VSC6134 also supports interfaces with most Intel processors.
Both synchronous and asynchronous interfaces are supported.
2.16.4.1
Intel Synchronous Mode
Interface
The following table lists the connections of the VSC6134 in this mode.
Table 68. Microprocessor Interface Signals in the Intel Synchronous Mode
Signal
Connection
MPU_CLK
ADSN
CSN
Function
MPU_CLK
ASN_ALE
CSN
Microprocessor clock
Address strobe
Chip select—Generated externally
Tied high
SYNSEL_DSN_WRN
RWN_WRN_RDN
MPMODE
MPSEL
1
WRN
Write/read
1
Select Synchronous mode
Select Intel
1
DTKN_RDY
INTN
RDYRCVN
INTN
Ready
Interrupt
DATA[15:0]
ADDR[11:0]
DATA[15:0]
ADDR[11:0]
Microprocessor data
Microprocessor address
183 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
