VSC6134
Datasheet
2.11
Frame Aligner for SONET, ODU, and OTU Frames
The frame aligner block detects the framing pattern on the incoming parallel input bus and performs
word and byte alignment. It outputs set-count, column-count and row-count, which provides basic
timing reference for the successive blocks. The frame aligner can be programmed to search for any of
the two patterns: A1A2A2 or A1A1A2A2. The block generates alarms when there is an error in the
framing pattern or when there is no framing pattern at the expected location for a specified amount of
time (OOF and LOF).
The frame aligner can be used in three modes: SONET mode, ODU mode, or OTU mode. The basic
operation of all the modes is the same. The difference between the three modes is the length of the
frame. In the SONET mode the frame period is 125 μs. In the ODU and OTU modes, the frame period is
12.191 μs for ODU2/OTU2 and 3.03 μs for ODU3/OTU3. The frame aligner block diagram is shown in
the following figure.
Figure 30. Frame Aligner Functional Block Diagram
DATA_INPUT
Pattern
Byte
Word
DATA_OUTPUT
Detector
Aligner
Aligner
Activate
Search
Pattern Detected
ODU_Mode
FEC_Mode
SEF
LOF
FSM
Sync
LOS
CLK
SYNCO
ROWCNT[3:0]
COLCNT[8 :0]
SETCNT[4:0]
Timing Generation
Word alignment takes place in two stages. The pattern detector searches for A1, A2 in the incoming data
and 15 bits of data coming on the next clock. Since the framing pattern may spread over two clocks,
15 bits of data coming on the second clock are taken to cover the case when 1 bit of the pattern is in the
nth clock, and the remaining 15 bits are in the (n + 1)th clock.
In the first stage, data is aligned for 16-bit boundary (depending on position of A1, A2 bytes). The task
of the second stage is to align the bytes to match the 8-byte word boundary, in case of a 64-bit wide data
bus (32-byte boundary in case of a 256-bit wide data bus). A state machine monitors framing error and
loss of framing pattern conditions and generates an appropriate alarm. Timing generation provides row
count, column count, and set-count for the successive blocks.The output ROWCNT signal indicates the
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
