VSC6134
Datasheet
2.8
Forward Error Correction (FEC) Decoder
The block diagram for the FEC decoder that exists on the drop line and add client sides of the VSC6134
is shown in the following figure.
Figure 20. FEC Decoder Block
OTU
Aligner
FEC
Descrambler
Clock
Crossing
FIFO
Reed Solomon
Interleaving
Buffer /
Reed Solomon
Decoder
Reed Solomon
Deinterleaving
Buffer
EFEC
Adapter
Enhanced FEC
BCH
Decoder
DWOH
RLL
Controller
PRBS
Monitor
Monitor /
FEC Error
Performance
Monitor
EFEC
Error Monitor
Mode
Adapter
Notes:
1. Bold arrows indicate 64-bit data paths.
2. Four data paths are available: Reed Solomon decoding, EFEC decoding, FEC bypass (for SDH or
transparent inputs), and EFEC monitoring mode (EFEC) decoder corrects and counts errors, but the
uncorrected data stream is passed through. Reed Solomon has error monitoring mode, but it does not use a
separate data path for this).
3. Shaded blocks are used only in drop path, implying there are only two data paths available and no
asynchronous capabilities using the RLL controller in the add path decoder.
The following functions are supported by the FEC decoder block.
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Clock domain crossing
16 × interleaving and deinterleaving for Reed Solomon
Digital wrapper overhead extraction and monitoring
BCH decoding (EFEC)
(255, 239) Reed Solomon decoding
Error monitoring mode (monitors but does not correct errors)
Complete FEC decoder bypass (SONET/SDH or transparent pass-through)
Optional G.709 or G.975 descrambling
FEC loopback
PRBS test monitoring mode
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
