DG540/541/542
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG541
Dual-In-Line and SOIC
IN
1
D
1
GND
S
1
V–
S
4
GND
D
4
DG542
Dual-In-Line and SOIC
IN
2
D
2
GND
S
2
V+
S
3
GND
D
3
IN
1
D
1
S
1
V–
GND
S
4
D
4
IN
4
1
2
3
4
5
6
7
8
Top View
16
15
14
13
12
11
10
9
IN
2
D
2
S
2
V+
GND
S
3
D
3
IN
3
1
2
3
4
5
6
7
8
Top View
16
15
14
13
12
11
10
9
TRUTH TABLE - DG541
Logic
0
1
Logic “0”
v
0.8 V
Logic “1”
w
2 V
TRUTH TABLE - DG542
Logic
0
1
Switch
OFF
ON
SW
1
, SW
2
OFF
ON
Logic “0”
v
0.8 V
Logic “1”
w
2 V
SW
3
, SW
4
ON
OFF
ORDERING INFORMATION
Temp Range
Package
Part Number
DG540
–40 to 85_C
20-Pin Plastic DIP
20-Pin PLCC
20-Pin Sidebraze
DG540DJ
DG540DN
DG540AP
DG540AP/883
–55 to 125_C
DG541
16-Pin Plastic DIP
–40 to 85_C
16-Pin Narrow SOIC
16-Pin Sidebraze
DG541DJ
DG541DY
DG541AP
–55 to 125_C
DG541AP/883, 5962-9076401MEA
DG542
–40 to 85_C
16-Pin Plastic DIP
16-Pin Narrow SOIC
16-Pin Sidebraze
DG542DJ
DG542DY
DG542AP
DG542AP/883, 5962-91555201MEA
Document Number: 70055
S-00399—Rev. G, 13-Sep-99
–55 to 125_C
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