DG534A/538A
Vishay Siliconix
SPECIFICATIONS
a
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
V+ = 15 V, V– = –3 V, V
L
= 5 V
WR = 0.8 V, RS, EN= 2 V
A Suffix
–55 to 125_C
D Suffix
–40 to 85_C
Temp
b
Typ
c
Min
d
Max
d
Min
d
Max
d
Unit
Dynamic Characteristics (Cont’d)
Chip Disabled Crosstalk
f
X
TALK(CD)
R
L
= 75
W ,
f = 5 MHz
EN = 0.8 V
See Figure 8
R
IN
= 10
W
R
L
= 10 kW
f = 5 MHz
SeeFigure 9
R
IN
= 75
W
, R
L
= 75
W
f = 5 MHz
See Figure 7
R
IN
= 10
W
R
L
= 10 kW
f = 5 MHz
See Figure 7
R
IN
= 75
W
, R
L
= 75
W
f = 5 MHz
See Figure 7
PLCC
DIP
PLCC
DIP
PLCC
DIP
PLCC
DIP
PLCC
DIP
Room
Room
Room
Room
Room
Room
Room
Room
Room
Room
Room
Room
Room
–75
–65
–97
–87
–80
–70
–77
–72
–77
–72
–84
–84
500
MHz
dB
Adjacent Input Crosstalk
f
X
TALK(AI)
All Hostile Crosstalk
X
TALK(AH)
R
IN
= 10
W
, R
L
= 10 kW
f = 5 MHz, See Figure 10
Differential Crosstalk
X
TALK(DIFF)
R
IN
= R
L
= 75
W
f = 5 MHz, See Figure 10
R
L
= 50
W
, See Figure 6
Bandwidth
BW
Power Supplies
Positive Supply Current
Negative Supply Current
Functional Check of
Maximum Operating
Supply Voltage Range
Logic Supply Current
I+
I–
V+ to V–
V– to GND
V+ to GND
I
L
Functional Test Only
Any One Channel Selected with Ad-
dress Inputs at GND or 5 V
Room
Full
Room
Full
Full
Full
Full
Full
150
0.6
0.6
–1.8
–2
10
–5.5
10
21
0
21
500
2
5
–1.8
–2
10
–5.5
10
21
0
21
500
mA
V
2
5
mA
Timing
Reset to Write
WR, RS
Minimum Pulse Width
A
0
, A
1
, EN
Data Valid to Strobe
A
0
, A
1
, EN
Data Valid after Strobe
Address Bus Tri-State
e
Address Bus Output
Address Bus Input
t
RW
t
MPW
t
DW
See Figure 1
t
WD
t
AZ
t
AO
t
AI
Room
Full
Room
Full
Room
Full
Room
Full
Room
Room
Room
–22
50
60
200
20
100
–20
50
25
95
110
50
100
ns
200
50
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Defined by system bus requirements.
f.
Each individual pin shown as GND must be grounded.
g. Guaranteed by design, not subject to production test.
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
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5
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