DG534A/538A
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG538ADJ
Dual-In-Line
GND
D
A
V+
S
A1
GND
S
A2
GND
S
A3
GND
1
2
3
4
5
6
7
8
9
28 D
B
S A1
V+
27 V–
26 S
B1
25 GND
24 S
B2
23 GND
22 S
B3
21 GND
20 S
B4
19 V
L
18 I/O
Latch/Drivers
17 EN
16 A
0
15 A
1
Top View
GND
S
A2
GND
S
A3
GND
S
A4
8/4
5
6
7
8
9
10
11
Latch/Drivers
12 13 14 15 16 17 18
WR
A2
RS
EN
I/O
A1
A0
25
24
23
22
21
20
19
GND
S
B2
GND
S
B3
GND
S
B4
V
L
DG538ADN
PLCC
DA
GND
S B1
DB
V–
4
3
2
1 28 27 26
S
A4
10
8/4 11
RS 12
WR 13
A
2
14
Top View
TRUTH TABLE
I/O
X
X
X
0
0
0
0
0
0
1
DG534A
4/2
a
1
X
X
0
0
0
0
1
1
Note c
None (latches cleared)
None
S
A1
S
A2
S
B1
S
B2
S
A1
and S
B1
S
A2
and S
B2
D
A
and D
B
may be
connected externally
A
1
X
X
X
0
0
1
1
X
X
A
0
X
X
X
0
1
0
1
0
1
Note b
EN
X
X
0
1
1
1
1
1
1
WR
X
0
0
0
0
0
0
0
1
RS
1
0
1
1
1
1
1
1
1
1
On Switch
Maintains previous state
Latches Transparent
Logic “0” = V
AL
v
0.8 V
Logic “1” = V
AH
w
2.4 V
X = Don’t Care
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Document Number: 70069
S-05734—Rev. G, 29-Jan-02
VISHAY [ VISHAY TELEFUNKEN ]
