PRELIMINARY
V•I Chip Bus Converter Module
Application Note (continued)
Input Impedance Recommendations
Anomalies in the response of the source will appear at the output of the
BCM multiplied by its K factor. The DC resistance of the source should be
kept as low as possible to minimize voltage deviations. This is especially
important if the BCM is operated near low or high line as the over/under
voltage detection circuitry could be activated.
To take full advantage of the BCM capabilities, the impedance presented
to its input terminals must be low from DC to approximately 5 MHz. The
source should exhibit low inductance (less than 100 nH) and should have a
critically damped response. If the interconnect inductance exceeds 100 nH,
the BCM input pins should be bypassed with an RC damper (e.g., 1 µF in
series with 0.3 ohm) to retain low source impedance and stable
Input Fuse Recommendations
operations. Given the wide bandwidth of the BCM, the source response is
generally the limiting factor in the overall system response.
V•I Chips are not internally fused in order to provide flexibility in
configuring power systems. However, input line fusing of V•I Chips must
always be incorporated within the power system. A fast acting fuse should
be placed in series with the +In port.
Applying the BCM
BCM
Vin = 360-400 Vdc
NS
NP
K=NS / NP
BCM
Vout = (Vin•K) – (Iout•Rout)
= 11.3-12.5 Vdc @ No load
= 11.0-12.2 Vdc @ Full load
NS
NP
B384F120T24
K = 1/32
Iout = 20 A @ 12 V
Rout = 13.9 mΩ
K=NS / NP
BCM
NS
NP
Paralleling
BCMs automatically current share
when connected in parallel.
No interconnections required.
K=NS / NP
Isolation Barrier
Standoff Voltage = 4,242 Vdc
Figure 24 — The BCM provides an isolated output proportional to its input. It is easily parallelable to create high power arrays and/or for N+M redundancy.
vicorpower.com
800-735-6200
V•I Chip Bus Converter Module
B384F120T24
Rev. 1.2
Page 11 of 13
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