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CD-700-SYNCE-25M0000000 参数 Datasheet PDF下载

CD-700-SYNCE-25M0000000图片预览
型号: CD-700-SYNCE-25M0000000
PDF下载: 下载PDF文件 查看货源
内容描述: 基于锁相环完整的VCXO [Complete VCXO Based Phase Lock Loop]
分类和应用: 石英晶振压控振荡器
文件页数/大小: 11 页 / 479 K
品牌: VECTRON [ Vectron International, Inc ]
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Performance Specifications
Table 1. Electrical Performance
Parameter
Output Frequency
OUT 1, 3.3 V option
OUT 2, 3.3V option
Supply Voltage
1
+3.3
Supply Current
Output Logic Levels
Output Logic High
2
Output Logic Low
2
Output Transition Times
Rise Time
2
Fall Time
2
Input Logic Levels
Input Logic High
2
Input Logic Low
2
Loss of Signal Indication
Output Logic High
2
Output Logic Low
2
Nominal Frequency on Loss of Signal
Output 1
Output 2
Symmetry or Duty Cycle
3
Out 1
Out 2
RCLK
Absolute Pull Range
over operating temperure, aging, and power
supply variations
Jitter Generation - 25 MHz output
(12kHz - 20MHz BW)
Test Conditions for APR (+3.3 V option)
Gain Transfer
Phase Detector Gain
+3.3 V
Operating temperature
Control Voltage Leakage Current
SYM1
SYM2
RCLK
APR
±100
V
DD
I
DD
V
OH
V
OL
t
R
t
F
V
IH
V
IL
V
OH
V
OL
2.0
0.5
2.5
0.5
±75
±75
40/60
45/55
40/60
2.5
0.5
3.0
3.0
2.97
Symbol
Min
Typical
50.0
25.0
3.3
Maximum
Units
MHz
MHz
3.63
63
V
mA
V
V
ns
ns
V
V
V
V
ppm
ppm
%
%
%
ppm
Φ
J
V
C
Kv
Kv
0.3
340
Positive
0.35
600
3.0
fsec-rms
V
rad/V
°C
±1.0
μA
T
OP
I
VCXO
-40/85
1. A 0.01uF and 0.1uF parallel capacitor should be located as close to pin 14 as possible (and grounded).
2. Figure 2 defines these parameters. Figure 3 illustrates the equivalent five gate TTL load and operating conditions under which these parameters
are tested and specified. Loads greater than 15 pF will adversely effect rise/fall time as well as symmetry.
3. Symmetry is defined as (ON TIME/PERIOD with Vs=1.4 V for both 5.0 V and 3.3 V operation.
Figure 2. Output Waveform
Figure 3. OUT1, OUT2, RCLK, RDATA Test Conditions (25 ±50C)
Page 2 of 11
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 15Dec2009