VN16118
Table 8. Receiver Timing Characteristics
TA = 0°C to +70°C, Vcc = 3.15 V to 3.45 V
Preliminary
Symbol
b_sync
f_lock
t
SETUP
t
HOLD
t
DUTY
t
A-B
T_rxlat
[2]
[1]
Parameter
Bit Sync Time
Frequency Lock at Powerup
Data Setup Before Rising Edge of RX_CLK
Data Hold After Rising Edge of RX_CLK
RX_CLK Duty Cycle
RX_CLK Skew
Receiver Latency
Min.
Typ.
Max.
2500
500
Unit
bits
µs
nsec
nsec
2.5
1.5
40
7.5
22.4
28.0
60
8.5
%
nsec
nsec
bits
Notes:
1. This is the recovery for input phase jumps.
2. The receiver latency as shown in Figure 6, is defined as the time between receiving the first serial bit of a
parallel data word (defined as the first edge of the first serial bit) and the clocking out of that parallel
word (defined by the rising edge of the receive byte clock, either RBC1 or RBC0).
t
SETUP
t
HOLD
RX_CLK<1>
1.4 V
2.0 V
K28.5
DATA
DATA
DATA
DATA
0.8 V
2.0 V
RX<9:0>
COM_DET
0.8 V
RX_CLK<0>
t
A-B
1.4 V
Figure 5. Receiver Section Timing
DATA BYTE C
DATA BYTE D
R2 R3 R4 R5
DIN±
R5 R6 R7 R8 R9 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
t_rxlat
RX<9:0>
DATA BYTE A
DATA BYTE D
RX_CLK<1>/<0>
1.4 V
Figure 6. Receiver Latency
1999-12-15
Page 9
MDSN-0001-00
Vaishali Semiconductor
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747 Camden Avenue
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Campbell
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CA 95008
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Ph. 408.379.2900
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Fax 408.379.2937
VAISH [ VAISHALI SEMICONDUCTOR ]
