VN16118
Table 1. Pin Description
Name
GND_ESD
VCC_ESD
TX<0>
TX<1>
TX<2>
TX<3>
TX<4>
TX<5>
TX<6>
TX<7>
TX<8>
TX<9>
GND_TXA
VCC_TXA
NC
Preliminary
Pin #
1, 14
5, 10
2
3
4
6
7
8
9
11
12
13
15
18
16, 17,
27, 48,
49
No
Connect
These pins are bonded to isolated pads and have no connection
to internal circuits.
Power
Power and ground pair for TX PLL analog circuits.
TTL
Input
10-bit parallel data input pins. This data should be 10b/8b
encoded. The least significant bit is TX<0> and is transmitted
first.
Type
Power
Description
Power and ground pairs for pad ESD structure.
EWRAP
19
TTL
Input
Wrap Enable. This pin is active HIGH. When asserted, the
high-speed serial data are internally wrapped from the transmitter
serial data output back to the receiver data input. Also, when
asserted, DOUT± are held static at logic 1. When deasserted,
DOUT± and DIN± are active.
Power and ground pair for TX digital circuits.
VCC_TXD
GND_TXD
TX_CLK
20
21
22
Power
TTL
Input
Reference clock and transmit byte clock. This is a 125 MHz
system clock supplied by the host system. On the positive edge
of the clock, the input data, TX<9:0>, are latched into the
register. This clock is multiplied by 10 internally, to generate the
transmit serial bit clock.
Power and ground pair for digital circuits in the receiver portion.
VCC_RXD
GND_RXD
EN_CDET
23 28,
25
24
Power
TTL
Input
Comma Detect Enable. This pin is active HIGH. When
asserted, the internal byte alignment function is turned on, to
allow the clock to synchronize with the comma character
(0011111XXX). When de-asserted, the function is disabled and
will not align the clock and data. In this mode COM_DET is set to
LOW.
Signal Detect. This pin is active HIGH. It indicates the loss of
input signal on the high-speed serial inputs, DIN±. SIG_DET is
set to LOW when differential inputs are less than 50 mV.
Power and ground pair for the clock signal of the receiver portion.
Receiver Byte Clocks. Two 180 degrees out-of-phase 62.5 MHz
clock signals that are recovered by the receiver section. The
received bytes are alternately clocked by the rising edges of
these signals. The rising edge of RX_CLK<1> aligns with a
comma character when detected.
SIG_DET
26
TTL
Output
Power
TTL
Output
VCC_RX
GND_RX
RX_CLK<1>
RX_CLK<0>
29
32
30
31
1999-12-15
Page 4
MDSN-0001-00
Vaishali Semiconductor
l
747 Camden Avenue
l
Campbell
l
CA 95008
l
Ph. 408.379.2900
l
Fax 408.379.2937
VAISH [ VAISHALI SEMICONDUCTOR ]
