VN16118
Table 6. Transceiver Reference Clock Requirements
T
A
= 0°C to +70°C, V
CC
= 3.15 V to 3.45 V
Preliminary
Symbol
f
F
tol
Symm
Parameter
Nominal Frequency (for gigabit Ethernet
Compliance)
Frequency Tolerance
Symmetry (Duty Cycle)
Min.
Typ.
125
Max.
Unit
MHz
-100
40
+100
60
ppm
%
Table 7. Transmitter Timing Characteristics
T
A
= 0°C to +70°C, V
CC
= 3.15 V to 3.45 V
Symbol
t
setup
t
hold
t_txlat
[1]
Parameter
Setup Time to Rising Edge of REFCLK
Hold Time to Rising Edge of REFCLK
Transmitter Latency
Min.
1.5
1.0
Typ.
Max.
Unit
nsec
nsec
3.5
4.4
nsec
bits
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the
parallel data word (as triggered by the rising edge of the transmit by clock, REFCLK) and the
transmission of the first serial bit of that parallel word (defined by the rising edge of the first bit
transmitted).
TX_CLK
1.4 V
2.0 V
TX<9:0>
DATA
t
SETUP
DATA
t
HOLD
DATA
DATA
DATA
DATA
0.8 V
Figure 3. Transmitter Section
Timing
DATA BYTE A
DATA BYTE B
DOUT± T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5
t_TXLAT
TX<9:0>
DATA BYTE B
DATA BYTE C
TX_CLK
1.4 V
Figure 4. Transmitter Latency
1999-12-15
Page 8
MDSN-0001-00
Vaishali Semiconductor
l
747 Camden Avenue
l
Campbell
l
CA 95008
l
Ph. 408.379.2900
l
Fax 408.379.2937
VAISH [ VAISHALI SEMICONDUCTOR ]
