UTC571
LINEAR INTEGRATED CIRCUIT
BASIC CIRCUIT HOOK-UP AND OPERATION
THD TRIM
R3
INVIN
5.12
8.9
6.11
R3
20K
R2
20K
G
IN
G
VREE
1.8V
3.14
OUTPUT
7.10
R4
30K
IG
R1
10K
VCC PIN 13
RECTIN
GND PIN 4
2.15
1.16
CRECT
Figure 2. Chip Block Diagram
Figure 2 shows the block diagram of one half of the chip, (there are two identical channels on the IC). The full-
wave averaging rectifier provides a gain control current, IG , for the variable gain (∆G) cell. The output of the DG
cell is a current which is fed to the summing node of the operational amplifier. Resistors are provided to establish
circuit gain and set the output DC bias.
The circuit is intended for use in single power supply systems, so the internal summing nodes must be biased at
some voltage above ground. An internal band gap voltage reference provides a very stable, low noise 1.8V
reference denoted VREF . The non-inverting input of the op amp is tied to VREF , and the summing nodes of the
rectifier and ∆G cell (located at the right of R1 and R2) have the same potential. The THD trim pin is also the VREF
potential.
R3
CIN1
R2
G
V
OUT
VIN
R4
V
REF
C
IN2
R1
2R3VIN (avg)
R1R2IB
NOTE: GAIN=
C
RECT
I
B
=140A
Figure 3. Basic Expander
Figure 3 shows how the circuit is hooked up to realize an expandor. The input signal, VIN is applied to the inputs
of both the rectifier and the ∆G cell. When the input signal drops by 6dB, the gain control current will drop by a
factor of 2, and so the gain will drop 6dB. The output level at VOUT will thus drop 12dB, giving us the desired 2 to 1
expansion.
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YOUW ANG ELECTRONICS CO.LTD
UTC [ Unisonic Technologies ]
