UTC571
LINEAR INTEGRATED CIRCUIT
FUNCTION DESCRIPTION
CIRCUIT DESCRIPTION
The UTC571 compandor building blocks, as shown in the block diagram, are a full-wave rectifier, a variable
gain cell, an operational amplifier and a bias system. The arrangement of these blocks in the IC result in a
circuit which can perform well with few external components, yet can be adapted to many diverse applications.
The full-wave rectifier rectifies the input current which flows from the rectifier input, to an internal summing
node which is biased at V REF . The rectified current is averaged on an external filter capacitor tied to the CRECT
terminal, and the average value of the input current controls the gain of the variable gain cell. The gain will thus
be proportional to the average value of the input signal for capacitively-coupled voltage inputs as shown in the
following equation. Note that for capacitively-coupled inputs there is no offset voltage capable of producing a
gain error. The only error will come from the bias current of the rectifier (supplied internally) which is less than
0.1µA.
| VIN − VREF | avg
G
G
or
R1
| VIN | avg
R1
The speed with which gain changes to follow changes in input signal levels is determined by the rectifier filter
capacitor. A small capacitor will yield rapid response but will not fully filter low frequency signals. Any ripple on
the gain control signal will modulate the signal passing through the variable gain cell. In an expander or
compressor application, this would lead to third harmonic distortion, so there is a trade-off to be made between
fast attack and decay times and distortion. For step changes in amplitude, the change in gain with time is shown
by this equation.
G(t)=(Ginitial-Gfinal)e-t/τ+Gfinal; τ=10k × CRECT
The variable gain cell is a current-in, current-out device with the ratio IOUT /IIN controlled by the rectifier. IIN is
the current which flows from the DG input to an internal summing node biased at VREF . The following equation
applies for capacitively-coupled inputs. The output current, IOUT , is fed to the summing node of the op amp.
VIN − VREF
VIN
R2
IIN =
=
R2
A compensation scheme built into the DG cell compensates for temperature and cancels out odd harmonic
distortion. The only distortion which remains is even harmonics, and they exist only because of internal offset
voltages. The THD trim terminal provides a means for nulling the internal offsets for low distortion operation.
The operational amplifier (which is internally compensated) has the non-inverting input tied to V REF , and the
inverting input connected to the DG cell output as well as brought out externally. A resistor, R 3 , is brought out
from the summing node and allows compressor or expander gain to be determined only by internal components.
The output stage is capable of ±20mA output current. This allows a +13dBm (3.5V RMS ) output into a 300W
load which, with a series resistor and proper transformer, can result in +13dBm with a 600Ω output impedance.
A bandgap reference provides the reference voltage for all summing nodes, a regulated supply voltage for the
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YOUW ANG ELECTRONICS CO.LTD
UTC [ Unisonic Technologies ]
