UTC571
LINEAR INTEGRATED CIRCUIT
VARIABLE GAIN CELL
V+
I1
140
A
R2
20K
Q1 Q2
I2(=2I1)
Q3 Q4
VIN
IIN
IG
280
A
V-
LG
IGVIN
Note: LOUT =
IIN =
L1
I2R2
Figure 9. Simplified ∆G Cell Schematic
Figure 9 is a diagram of the variable gain cell. This is a linearized two-quadrant transconductance multiplier. Q 1 ,
Q 2 and the op amp provide a predistorted drive signal for the gain control pair, Q 3 and Q 4 . The gain is
controlled by I G and a current mirror provides the output current.
The op amp maintains the base and collector of Q 1 at ground potential (V REF ) by controlling the base of Q 2 .
The input current I IN (=V IN /R 2 ) is thus forced to flow through Q 1 along with the current I 1 , so I C1 =I 1 +I IN .
Since I 2 has been set at twice the value of I 1 , the current through Q 2 is:
I2 - (I1 +IIN ) = I1 - IIN = IC2.
The op amp has thus forced a linear current swing between Q 1 and Q 2 by providing the proper drive to the
base of Q 2 . This drive signal will be linear for small signals, but very non-linear for large signals, since it is
compensating for the non-linearity of the differential pair, Q 1 and Q 2 , under large signal conditions.
The key to the circuit is that same predistorted drive signal is applied to the gain control pair, Q3 and Q4. When
two differential pairs of transistors have the same signal applied, their collector current ratios will be identical
regardless of the magnitude of the currents. This gives us :
IC1
IC2
IC4
IC3
I1 + IIN
I1 − IIN
=
=
plus the relationships IG = IC3 + IC4 and IOUT = IC4 − IC3 will yield the multiplier transfer function,
IG
I1
VINIG
R2I1
IOUT =
IIN =
This equation is liner and temperature-insenstive, but it assumes ideal transistor.
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YOUW ANG ELECTRONICS CO.LTD
UTC [ Unisonic Technologies ]
