UTC571
LINEAR INTEGRATED CIRCUIT
4
3
VOS=5mV
4mV
2
3mV
2mV
1
1mV
0.34
-6
0
+6
INPUT LEVEL(dBm)
Figure 10. ∆G Cell Distortion vs Offset Voltage
If the transistors are not perfectly matched, a parabolic, non-linearity is generated, which results in second
harmonic distortion. Figure 10 gives an indication of the magnitude of the distortion caused by a given input level
and offset voltage. The distortion is linearly proportional to the magnitude of the offset and the input level.
Saturation of the gain cell occurs at a +8dBm level. At a nominal operating level of 0dBm, a 1mV offset will yield
0.34% of second harmonic distortion. Most circuits are somewhat better than this, which means our overall offsets
are typically about mV. The distortion is not affected by the magnitude of the gain control current, and it does not
increase as the gain is changed. This second harmonic distortion could be eliminated by making perfect transistors,
but since that would be difficult, we have had to resort to other methods. A trim pin has been provided to allow
trimming of the internal offsets to zero, which effectively eliminated second harmonic distortion. Figure 11 shows
the simple trim network required.
VCC
R
3.6V
20K
6.2K
TO THD
TRIM
200PF
Figure 11. THD Trim Network
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YOUW ANG ELECTRONICS CO.LTD
UTC [ Unisonic Technologies ]
