GA1086
AC Specifications
Figure 11. Switching Waveforms
(Supply voltage: +5 V + 5%, Ambient temp: 0 °C to +70 °C) Buffer Configuration (FBIN = FBOUT)
Input Clocks
Min
Typ
Max Unit
t
t
CPW
CPW
REFCLK
FBIN
FIN
tCP
CLK frequency
30
14.9
3.0
—
—
—
—
—
67
33
—
MHz
ns
CLK period
t
t
JR
tCPW
tIR
CLK pulse width
Input rise time (0.8 V – 2.0 V)
ns
PD1,2
2.0
ns
t
PERIOD
Q0 – Q10
(INDIVIDUALLY)
t
JP
Output Clocks
Min
Typ
Max Unit
tOR
tOF
Output rise time (0.8 V – 2.0 V) 0.15
Output fall time (0.8 V – 2.0 V) 0.15
—
—
1.4
1.4
ns
ns
ps
ps
ps
ps
ps
ns
ps
ns
µs
ps
1
tPD1
CLK Î to FBIN Î (MC500)
CLK Î to FBIN Î (MC1000)
–850
–1350
–125
–125
–125
—
–350
–350
—
+150
+650
+125
+125
+125
1.2
1,2
tPD2
Figure 12. AC Test Circuit
2,3
tSKEW1 Q1–Q9 and FBOUT (0.8V)
2,3
tSKEW1 Q1–Q9 and FBOUT (1.5V)
—
2,3
tSKEW1 Q1–Q9 and FBOUT (2.0V)
—
Y
2,3
+5 V
R1
+5 V
tSKEW2 Q/2 Output skew
0.6
100
1.0
200
75
50 Ω
X
4
tW
Output window
—
250
—
R1
R2
Z
+5 V
5
Q0
Q1
Q2
•
•
•
tCYC
Duty-cycle variation
Synchronization time
Period-to-period jitter
—
FBIN
CLK
R1
R2
R2
6
tSYNC
—
500
—
7
•
tJIT
—
+5 V
R1
•
•
•
+5 V
R1
Z
•
Q10
R2
R2
Notes:
R1 = 160 Ω
R2 = 71 Ω
Y + Z = X
Notes: 1. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty
cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN.
2. tPD and tSKEW are tested with an input clock having a rise time of 0.5 ns (0.8 V to 2.0 V).
3. The output skew is measured from the middle of the output window, tW. The maximum skew is guaranteed across all voltages and
temperatures.
4. tW specifies the width of the window in which outputs Q1–Q9 switch.
5. This specification represents the deviation from 50/50 on the outputs; it is sampled periodically but is not guaranteed.
6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and a connection from one of the
outputs to FBIN.
7. Jitter is specified as a peak-to-peak value.
10
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