AH225
1W High Linearity InGaP HBT Amplifier
Pin Description
Pin 1 Reference Mark
Vbias
N/C
1
2
3
4
8
7
6
5
Iref
RF_Out
RF_Out
N/C
RF_In
N/C
Backside Paddle - RF/DC GND
Pin
1
Symbol
Vbias
Description
Voltage supply for active bias. Connect to same supply voltage as Vcc.
No internal connection. This pin can be grounded or N/C on PCB.
RF Input. Requires matching for operation.
2, 4, 5
N/C
3
6
7
RF_in
RF_out
RF_out
RF Output and DC supply voltage.
See pin 6.
Reference current into internal active bias current mirror. Current into Iref sets device
quiescent current. Also, can be used as on/off control.
Use recommended via pattern shown on page 20 and ensure good solder attach for
optimum thermal and electrical performance.
8
Iref
Backside
Paddle
RF/DC GND
Application Board Information
PC Board Layout
Top RF layer is .014” Getek, єr = 4.0, 4 total layers
(0.062” thick) for mechanical rigidity. Metal layers are 1-
oz copper. Microstrip line details: width = .030”, spacing
= .026”.
The silk screen markers ‘A’, ‘B’, ‘C’, etc. and ‘1’, ‘2’, ‘3’,
etc. are used as placemarkers for the input and output
tuning shunt capacitors – C8, C5 and C2. The markers
and vias are spaced in .050” increments.
The pad pattern shown has been developed and tested for
optimized assembly at TriQuint Semiconductor. The PCB
land pattern has been developed to accommodate lead and
package tolerances. Since surface mount processes vary
from company to company, careful process development
is recommended.
For
www.TriQuint.com
further
technical
information,
Refer
to
Data Sheet: Rev F 05/17/12
Disclaimer: Subject to change without notice
- 19 of 21 -
© 2012 TriQuint Semiconductor, Inc.
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