AH225
1W High Linearity InGaP HBT Amplifier
Application Circuit 2110-2170 MHz (AH225-S8PCB2140)
Notes:
1. See PC Board Layout, page 20 for more information.
2. Vref J4 turret can be used as control voltage for device power down (low = RF off) by setting R8 = 0 ꢀ and R8 = no connect.
3. The primary RF microstrip characteristic line impedance is 50 ꢀ.
4. Do not exceed +5.5V on Vpd or Vcc or TVS diode D3 will be damaged.
5. Components shown on the silkscreen but not on the schematic are not used.
6. The edge of L2 is placed at 205 mils from the edge of Ah225 RFin pin pad (23° at 2140 MHz).
7. The edge of C9 is placed at 80 mils from the edge of AH225 RFin pin pad (9° at 2140 MHz).
8. The edge of C2 is placed at 205 mils from the edge of AH225 RFout pin pad (23° at 2140 MHz).
9. The edge of C6 is placed at 80 mils from the edge of AH225 RFout pin pad (9° at 2140 MHz).
10. Zero ohm jumpers may be replaced with copper traces in the target application layout.
11. DNP means Do Not Place.
12. Inductor L3 on Vpd line is critical for linearity performance.
13. The locations of C11, R2, C10 and C3 are non-critical. They can be placed closer to the device.
14. Ferrite Bead FB1 eliminates bypass line resonances between C15 and C1. Steward MI0603K300R-10.
15. All components are of 0603 size unless stated otherwise.
Typical Performance 2110-2170 MHz
Frequency
Gain
MHz
dB
dB
2110
15.2
20
2140
15.5
18
2170
15.6
17
Input Return Loss
Output Return Loss
Output P1dB
dB
7.7
9.4
12
dBm
dBm
dBm
dB
+31.5
+45.6
+20.9
6
+31.2
+46
+21.3
6
+31.1
+46.1
+21
Output IP3 at 19 dBm/tone, ∆f = 1 MHz
WCDMA Channel Power at -50 dBc ACLR [1]
Noise Figure
5.9
Supply Voltage, Vcc
Quiescent Collector Current, Icq
V
mA
+5
300
Notes:
1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, +5 MHz offset, PAR = 10.2 dB at 0.01% Prob.
Data Sheet: Rev F 05/17/12
Disclaimer: Subject to change without notice
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© 2012 TriQuint Semiconductor, Inc.
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