Tripath Technology, Inc. – Preliminary Technical Information
3. On the ninth SCK pulse, the master releases SDA and the slave acknowledges by pulling SDA
LOW.
4. The slave holds SCK low until it is ready to receive the next byte.
5. The slave releases SCK and the master begins toggling SCK and transmits the control register
address on SDA.
6. On the ninth SCK pulse, the master releases SDA and the slave acknowledges by pulling SDA
LOW.
7. The slave holds SCK low until it is ready to receive the next byte.
8. The slave releases SCK and the master begins toggling SCK and transmits the data byte on
SDA.
9. On the ninth SCK pulse, the master releases SDA and the slave acknowledges by pulling SDA
LOW.
10. The slave holds SCK low until it is ready to receive the next byte.
11. To transmit additional data bytes, repeat steps 8 through 10.
12. A stop condition is generated when SCK is released and SDA goes HIGH while SCK is still
high.
When the master reads data from the slave, the following events occur:
0. SDA and SCK are both HIGH.
1. A start condition is generated when the master pulls SDA LOW.
2. The master begins toggling SCK and transmits the slave’s device address on SDA with a 1 in
the LSB (ex. 81h).
3. On the ninth SCK pulse, the master releases SDA and the slave acknowledges by pulling SDA
LOW.
4. The slave holds SCK low until it is ready to receive the next byte.
5. The slave releases SCK and the master begins toggling SCK and transmits the control register
address on SDA.
6. On the ninth SCK pulse, the master releases SDA and the slave acknowledges by pulling SDA
LOW.
7. The slave holds SCK low until it is ready to transmit data.
8. The slave releases SCK and the master begins toggling SCK and the slave transmits the data
byte on SDA.
9. On the ninth SCK pulse, the slave releases SDA and the master acknowledges by pulling SDA
LOW.
10. The slave holds SCK low until it is ready to transmit the next byte.
11. To read additional data bytes, repeat steps 8 through 10.
12. A stop condition is generated when SCK is released and SDA goes HIGH while SCK is still
high.
When writing to the TCD6001, the first data byte after the device address is a sub-address. Subsequent
data will be written to TCD6001 control registers referred to by the sub-address. When reading from the
TCD6001, data will be read starting from the most recently written sub-address.
Control registers from sub-addresses 00h through 7Fh can also be accessed at sub-addresses 80h through
FFh. The difference is that sub-addresses 80h through FFh are auto-increment registers. Repeated reads
and writes to these registers will automatically increment the sub-address.
For example, if a microcontroller wanted to write a value of E6h to all of the volume registers, it would write
the following bytes through its I2C port: <start> 80h A5h E6h E6h E6h E6h E6h E6h <stop>. If it wanted to
read those values back it would send: <start> 80h A5h <stop> <start> 81h <read> <read> <read> <read>
<read> <read> <stop>.
16
TCD6001 – JL/Rev. 0.9/07.05
TRIPATH [ TRIPATH TECHNOLOGY INC. ]
