Tripath Technology, Inc. – Preliminary Technical Information
TCD6001 Operation Overview
POWER SUPPLY
The TCD6001 requires both 3.3V and 5V supplies. Pins labeled VD33 correspond to the digital power
networks, and pins labeled VA33 and VA50 correspond to the analog power networks. All should be
separately decoupled to their respective grounds.
All TCD6001 logic inputs are 3.3V unless otherwise specified.
VD18EN
VD18EN is a logic input that enables the internal 1.8V regulator. It should be tied to VD33.
REXT
The REXT pin should be connected to ground through an external 10KΩ. This connection is used by the
TCD6001 as a current reference. The 10KΩ resistor must have an accuracy of +/- 1%.
V2BG and V2BGFILT
The V2BG and V2BGFILT pin should each be AC coupled to GA with a 0.1uF capacitor.
RESETB
When pulled low, the RESETB pin will force all control registers from sub-address 00h to 6Fh and 80h to
EFh to their default state. Registers from sub-address 70h to 7Fh and F0h to FFh remain unchanged.
FAULT
The TCD6001 has the ability to detect Over and Under-voltage faults via external sense resistors. The
TCD6001 does not detect over current or over temperature faults. These are expected to be done
externally. However, a FAULT input has been provided as an alternate "mute" input. The default (non-
muted) state for FAULT is “floating”. The pin will self-bias to approximately 2.5V. If FAULT is taken to either
5V or 0V the TCD6001 will go in to hard mute. If FLD (register 3Ah bit D2) is set to ‘1’, the TCD6001 will
automatically un-mute after FAULT is released (forced or floated back to 2.5V). If FLD is cleared to ‘0’, the
TCD6001 will remain latched in this FAULT-based muted condition until the FAULT pin is released and FLC
(register 3Ah bit D1) undergoes a ‘0’ to ‘1’ transition.
AUTOMATIC DC OFFSET CALIBRATION
When the TCD6001 comes out of hard mute (register 2Ch bit D1 transitions from ‘1’ to ‘0’) an automatic DC
offset calibration sequence is started. During this sequence, the TCD6001 calibrates itself and its external
components to minimize DC offset at the speaker outputs that can be caused by process variations and
component tolerance.
The automatic DC offset calibration sequence takes a maximum of 1 second if the PGC is disabled and 4
seconds if the PGC is enabled. The additional time is required because each different amplifier gain level
may require a different calibration level. Therefore, each of the four PGC levels will require calibration upon
un-muting.
Automatic DC offset calibration produces 10 bit offset values for each channel that are stored in internal
registers. When Automatic DC offset calibration is enabled, the 10 bit values that are in use can be read in
the Calibration Readback registers (registers 02h – 09h). When the PGC is enabled, four different values
are stored for each channel. The values that are seen in the Calibration Readback registers will change as
the PGC Setting changes.
13
TCD6001 – JL/Rev. 0.9/07.05
TRIPATH [ TRIPATH TECHNOLOGY INC. ]
