Tripath Technology, Inc. – Preliminary Technical Information
Special care should be taken when using this scheme to prevent events from interfering with DC calibration.
FAULT should be latched so that a proper calibration can take place during un-mute. Clocks should be kept
synchronized to prevent automatic reset.
I2C INTERFACE
The I2C interface is a simple bi-directional bus interface for allowing a microcontroller to read and write
control registers in the TCD6001. Every component hooked up to the I2C bus has its own unique address
whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver
and/or transmitter depending on its functionality. The TCD6001 acts as a slave while a microcontroller would
act as a master.
The TCD6001 device address is 80h, 82h, 84h, or 86h depending on the state of the ADDRn pins. The
TCD6001 constantly monitors the I2C data input and waits until its device address appears before writing
into or reading from its control registers. The 8th bit of the address determines whether the master is reading
or writing. When the last bit is HIGH, the master is reading from a register on the slave. When the last bit is
LOW, the master is writing to a register on the slave.
ADDR2
ADDR1 TCD6001 write TCD6001 read
address
address
0
0
1
1
0
1
0
1
80h
82h
84h
86h
81h
83h
85h
87h
The I2C interface consists of a serial data input (SDA) and a clock input (SCK) and is capable of both
reading and writing. Both SCK and SDA are bi-directional lines connected to VD33 via a pull-up resistor.
When the bus is free both lines are HIGH.
The SCK clock frequency is typically less than 400 kHz. Data is transmitted serially in groups of 8 bits,
followed by an acknowledge bit. The data on the SDA line is expected to be stable while SCK is HIGH.
SCK
SDA
A7
A6
A5
A4
A3
A2
A1
R/W
D7
D6
D5
D4
D3
D2
D1
D0
start
ACK
ACK
stop
A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH.
After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted
after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the
master is receiving data from the slave or transmitting data to the slave. When an address is sent, each
device in the system compares the first seven bits after a start condition with its address. If they match, the
device considers itself addressed by the master. Data transfer with acknowledge is obligatory. The
transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data
line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver
which has been addressed is obliged to generate an acknowledge after each byte of data has been
received. The receiver can hold the SCK line LOW after an acknowledge to force the transmitter to wait until
the receiver is ready to accept another byte.
When addressed as a slave, the following protocol must be adhered to, once a slave acknowledge has been
returned, an 8-bit sub-address will be transmitted. If the LSB of the slave address was ‘1’, a repeated
START condition will have to be issued after the address byte; if the LSB is ‘0’ the master will transmit to the
slave with direction unchanged.
When the master writes data to the slave, the following events occur:
0. SDA and SCK are both HIGH.
1. A start condition is generated when the master pulls SDA LOW.
2. The master begins toggling SCK and transmits the slave’s device address on SDA with a 0 in
the LSB (ex. 80h).
15
TCD6001 – JL/Rev. 0.9/07.05
TRIPATH [ TRIPATH TECHNOLOGY INC. ]
