TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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6.2 Overview of Available Chip Features
The following table shows EtherCAT chip features available in TRINAMIC’s EtherCAT slave controller solu-
tions.
Chip Feature / Description
Domain
Register
Register
Register
Register
Register
Register
Register
Register
Register
Extended DL control register 0x0102:0x0103 enabled
AL Status code register 0x0134:0x0135 enabled
ECAT interrupt mask 0x0200:0x0201 enabled
Configured station alias 0x0012:0x0013 enabled
General purpose inputs 0x0F18:0x0F1F enabled
General purpose outputs 0x0F10:0x0F17 enabled
AL event mask 0x0204:0x0207 enabled
1
1
1
1
0
0
1
0
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
0
0
1
0
0
0
Physical RD/WR offset 0x0108:0x0109 enabled
Bridge port PDI (0x07) enabled
Writable Watchdog divider 0x0400:0x0401 and Watchdog PDI Watchdog
0x0410:0x0411 enabled
Watchdog counters 0x0442:0x0444 enabled
ECAT write protection 0x0020:0x0031 enabled
Reset registers 0x0040:0x0041 enabled
FPGA update at 0x0E00 enabled
Watchdog
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
0
1
0
0
0
Ext. Function
Ext. Function
Ext. Function
Ext. Function
DC Sync event times enabled
ECAT processing unit and PDI error counters/PDI error code Ext. Function
0x030C:0x030E enabled
User RAM disabled
Ext. Functions
Ext. Functions
PHY Layer
PHY layer
1
0
0
1
1
1
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
1
0
1: POR Values, 0: VENDOR ID
EEPROM control by PDI enabled
Lost link counters 0x0310:0x0313 enabled
MII management interface 0x0510 enabled
Enhanced link detection for MII enabled
Link detection and configuration for MII enabled
PDI support for MII management interface enabled
Automatic MII TX shift enabled
PHY layer
PHY layer
PHY layer
PHY layer
PHY layer
Extended RX Error counter registers 0x0314:0x0317 and PHY layer
0x0320:0x0327 enabled
RUN LED enabled
LEDs
1
1
1
1
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