TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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7.3.4.18 Register 35 – SD_CFG
Bit
0
Description
ECAT
PDI
-/w
-/w
Range [Unit]
0/1 = disable/enable SD_CH0
-/w
1
0
=
generate
N
pulses based on -/w
SD_CH0_STEPTARGET register value
1 = continuous mode
2
3
4
5
6
S0 and S0n step pulse signal polarity
D0 and D0n direction signal polarity
1 = clears SD_CH0_STEPCOUNT
reserved
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
use SD_CH0_NEXTSR for SD_CH0_STEPRATE on -/w
compare event
7
8
9
reserved
-/w
-/w
-/w
-/w
-/w
0/1 = disable/enable SD_CH1
0
=
generate
N
pulses based on -/w
SD_CH1_STEPTARGET register value
1 = continuous mode
10
11
12
13
14
S1 and S1n step pulse signal polarity
D1 and D1n direction signal polarity
1 = clears SD_CH1_STEPCOUNT
reserved
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
use SD_CH1_NEXTSR for SD_CH1_STEPRATE on -/w
compare event
15
16
17
reserved
-/w
-/w
-/w
-/w
-/w
0/1 = disable/enable SD_CH2
0
=
generate
N
pulses based on -/w
SD_CH2_STEPTARGET register value
1 = continuous mode
18
19
20
21
22
S2 and S2n step pulse signal polarity
D2 and D2n direction signal polarity
1 = clears SD_CH2_STEPCOUNT
reserved
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
-/w
use SD_CH2_NEXTSR for SD_CH2_STEPRATE on -/w
compare event
23
reserved
-/w
-/w
Table 160: MFC IO Register 35 – SD_CFG
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