TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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7.3.4.15 Register 32 – SD_CH2_NEXTSR
Bit
Description
ECAT
PDI
Range [Unit]
31:0
Next accumulation constant that will be written -/w
to SD_CH2_STEPRATE at compare event.
-/w
0. . . +(232) − 1
Table 157: MFC IO Register 32 – SD_CH2_NEXTSR
7.3.4.16 Register 33 – SD_STEPLENGTH
Bit
Description
ECAT
PDI
Range [Unit]
15:0
Configurable step pulse length for SD_CH0 in -/w
terms of 25MHz clock cycles.
-/w
0. . . +(216) − 1
31:16 Configurable step pulse length for SD_CH1 in -/w
-/w
-/w
0. . . +(216) − 1
0. . . +(216) − 1
terms of 25MHz clock cycles.
47:32 Configurable step pulse length for SD_CH2 in -/w
terms of 25MHz clock cycles.
Table 158: MFC IO Register 33 – SD_STEPLENGTH
Note
Maximum step length: The individual step pulse length tST EP _P ULSE [s] must be
lower than the time tST EP [s] between step pulses to actually see step pulses. The
condition tST EP _P ULSE < tST EP must be ensured by the application.
Also refer to Section 7.14 for more details and formulas for calculation.
7.3.4.17 Register 34 – SD_DELAY
Bit
Description
ECAT
PDI
Range [Unit]
15:0
Configurable step-to-direction delay for -/w
SD_CH0 in terms of 25MHz clock cycles.
-/w
0. . . +(216) − 1
31:16 Configurable step-to-direction delay for -/w
-/w
-/w
0. . . +(216) − 1
0. . . +(216) − 1
SD_CH1 in terms of 25MHz clock cycles.
47:32 Configurable step-to-direction delay for -/w
SD_CH2 in terms of 25MHz clock cycles.
Table 159: MFC IO Register 34 – SD_DELAY
Note
Step-to-direction delay is the delay between the first step pulse after a change of
the direction.
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