TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
20
5.1 General Configuration Registers
GENERAL CONFIGURATION REGISTERS (0X00…0X1F)
R/W
Addr
n
Register
Description / bit names
Bit GCONF – Global configuration flags
0..2 Reserved, set to 0
poscmp_enable
3
0:
1:
Outputs INT and PP are tristated.
Position compare pulse (PP) and interrupt output
(INT) are available
Attention – do not leave the outputs floating in tristate
condition, provide an external pull-up or set this bit 1.
4..6 Reserved, set to 0
7
test_mode
RW
0x00
11
GCONF
0:
1:
Normal operation
Enable analog test output on pin REFR2
TEST_SEL selects the function of REFR2:
0…4: T120, DAC1, VDDH1, DAC2, VDDH2
Attention: Not for user, set to 0 for normal operation!
shaft1
8
9
1:
shaft2
1: Inverse motor 2 direction
10 lock_gconf
Inverse motor 1 direction
1:
GCONF is locked against further write access.
Bit
GSTAT – Global status flags
0
1
reset
1:
Indicates that the IC has been reset since the last
read access to GSTAT.
drv_err1
1: Indicates, that driver 1 has been shut down due
to overtemperature or short circuit detection
since the last read access. Read DRV_STATUS1 for
details. The flag can only be reset when all error
conditions are cleared.
R+C
0x01
4
GSTAT
2
3
drv_err2
1:
Indicates, that driver 2 has been shut down due
to overtemperature or short circuit detection
since the last read access. Read DRV_STATUS2 for
details. The flag can only be reset when all error
conditions are cleared.
uv_cp
1:
Indicates an undervoltage on the charge pump.
The driver is disabled in this case.
Bit
3..0 TEST_SEL:
selects the function of REFR2 in test mode:
SLAVECONF
W
R
0x03
0x04
4
TEST_SEL
INPUT
0…4: T120, DAC1, VDDH1, DAC2, VDDH2
Attention: Not for user, set to 0 for normal operation!
Bit
INPUT
0..6 Unused, ignore these bits
8
+
8
7 Reads the state of the DRV_ENN pin
31.. VERSION: 0x01=first version of the IC
24 Identical numbers mean full digital compatibility.
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