TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
17
Example:
For a read access to the register (XACTUAL) with the address 0x21, the address byte has to
be set to 0x21 in the access preceding the read access. For a write access to the register
(VMAX), the address byte has to be set to 0x80 + 0x27 = 0xA7. For read access, the data bit
might have any value (-). So, one can set them to 0.
action
data sent to TMC5031 data received from TMC5031
read XACTUAL
read XACTUAL
write VMAX:= 0x00ABCDEF
write VMAX:= 0x00123456
0x2100000000
0x2100000000
0xA700ABCDEF
0xA700123456
0xSS & unused data
0xSS & XACTUAL
0xSS & XACTUAL
0xSS00ABCDEF
*)S: is a placeholder for the status bits SPI_STATUS
4.1.2 SPI Status Bits Transferred with Each Datagram Read Back
New status information becomes latched at the end of each access and is available with the next SPI
transfer.
SPI_STATUS – status flags transmitted with each SPI access in bits 39 to 32
Bit Name
Comment
7
6
5
4
3
2
1
0
-
reserved (0)
status_stop_l(2)
status_stop_l(1)
velocity_reached(2)
velocity_reached(1)
driver_error(2)
driver_error(1)
reset_flag
RAMP_STAT2[0] – 1: Signals motor 2 stop left switch status
RAMP_STAT1[0] – 1: Signals motor 1 stop left switch status
RAMP_STAT2[8] – 1: Signals motor 2 has reached its target velocity
RAMP_STAT1[8] – 1: Signals motor 1 has reached its target velocity
GSTAT[2] – 1: Signals driver 2 driver error (clear by reading GSTAT)
GSTAT[1] – 1: Signals driver 1 driver error (clear by reading GSTAT)
GSTAT[0] – 1: Signals, that a reset has occurred (clear by reading GSTAT)
4.1.3 Data Alignment
All data are right aligned. Some registers represent unsigned (positive) values, some represent integer
values (signed) as two’s complement numbers, single bits or groups of bits are represented as single
bits respectively as integer groups.
4.2 SPI Signals
The SPI bus on the TMC5031 has four signals:
-
-
-
-
SCK – bus clock input
SDI – serial data input
SDO – serial data output
CSN – chip select input (active low)
The slave is enabled for an SPI transaction by a low on the chip select input CSN. Bit transfer is
synchronous to the bus clock SCK, with the slave latching the data from SDI on the rising edge of SCK
and driving data to SDO following the falling edge. The most significant bit is sent first. A minimum
of 40 SCK clock cycles is required for a bus transaction with the TMC5031.
If more than 40 clocks are driven, the additional bits shifted into SDI are shifted out on SDO after a
40-clock delay through an internal shift register. This can be used for daisy chaining multiple chips.
CSN must be low during the whole bus transaction. When CSN goes high, the contents of the internal
shift register are latched into the internal control register and recognized as a command from the
master to the slave. If more than 40 bits are sent, only the last 40 bits received before the rising edge
of CSN are recognized as the command.
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