TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
16
4 SPI Interface
4.1 SPI Datagram Structure
The TMC5031 uses 40 bit SPI™ (Serial Peripheral Interface, SPI is Trademark of Motorola) datagrams
for communication with a microcontroller. Microcontrollers which are equipped with hardware SPI are
typically able to communicate using integer multiples of 8 bit. The NCS line of the TMC5031 must be
handled in a way, that it stays active (low) for the complete duration of the datagram transmission.
Each datagram sent to the TMC5031 is composed of an address byte followed by four data bytes. This
allows direct 32 bit data word communication with the register set of the TMC5031. Each register is
accessed via 32 data bits even if it uses less than 32 data bits.
For simplification, each register is specified by a one byte address:
-
For a read access the most significant bit of the address byte is 0.
-
For a write access the most significant bit of the address byte is 1.
Most registers are write only registers, some can be read additionally, and there are also some read
only registers.
TMC5031 SPI DATAGRAM STRUCTURE
MSB (transmitted first)
40 bit
LSB (transmitted last)
... 0
39 ...
8 bit address
8 bit SPI status
39 ... 32
32 bit data
31 ... 0
to TMC5031:
RW + 7 bit address
from TMC5031:
8 bit SPI status
39 / 38 ... 32
8 bit data
31 ... 24
8 bit data
23 ... 16
8 bit data
15 ... 8
8 bit data
7 ... 0
W
38...32
31...28
27...24
23...20
19...16
15...12
11...8
7...4
3...0
3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
4.1.1 Selection of Write / Read (WRITE_notREAD)
The read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI
datagram). This bit is 0 for read access and 1 for write access. So, the bit named W is a
WRITE_notREAD control bit. The active high write bit is the MSB of the address byte. So, 0x80 has to
be added to the address for a write access. The SPI interface always delivers data back to the master,
independent of the W bit. The data transferred back is the data read from the address which was
transmitted with the previous datagram, if the previous access was a read access. If the previous
access was a write access, then the data read back mirrors the previously received write data. So, the
difference between a read and a write access is that the read access does not transfer data to the
addressed register but it transfers the address only and its 32 data bits are dummies, and, further the
following read or write access delivers back the data read from the address transmitted in the
preceding read cycle.
A read access request datagram uses dummy write data. Read data is transferred back to the master
with the subsequent read or write access. Hence, reading multiple registers can be done in a
pipelined fashion.
Whenever data is read from or written to the TMC5031, the MSBs delivered back contain the SPI
status, SPI_STATUS, a number of eight selected status bits.
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