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TMC223 DATASHEET (V. 1.05 / March 7, 2011)
6 Two-Wire Serial Interface
6.1 Physical Layer
Both SDA and SCL lines are connected to positive supply voltage via a current source or pull-up
resistor (see figure below). When there is no traffic on the bus both lines are high. Analog glitch filters
are implemented to suppress spikes with a length of up to 50 ns.
+ 5V
SDA line
SCL line
SCL_IN
SCL_IN
SDA_IN
SDA_IN
SCL_OUT
SDA_OUT
SCL_OUT
SDA_OUT
TMC222
Master
Figure 14: Two Wire Serial Interface - Physical Layer
6.2 Communication on Two Wire Serial Bus Interface
Each datagram starts with a Start condition and ends with a Stop condition. Both conditions are unique
and cannot be confused with data. A high to low transition on the SDA line while SCL is high indicates
a Start condition. A low to high transition on the SDA line while SCL is high defines a Stop condition
(see figure below).
SDA
SCL
STOP
condition
START
condition
Figure 15: Two Wire Serial Interface - Start / Stop Conditions
The SCL clock is always generated by the master. On every rising transition of the SCL line the data
on SDA is valid. Data on SDA line is only allowed to change as long as SCL is low (see figure below).
SDA
SCL
data line
stable,
data valid
data change
allowed
Figure 16: Two Wire Serial Interface - Bit transfer
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TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
