TMC223 DATASHEET (V. 1.05 / March 7, 2011)
29
6.6 Timing characteristics of the serial interface
START
START
STOP
START
SDA
SCL
tf
tLOW
tr
tSU;DAT tf
tHD;STA
tr
tBUF
tHD;STA
tHD;DAT tHIGH
tSU;STA
tSU;STO
Figure 21: Definition of Timing
SCL Clk frequency <= 100KHz
SCL Clk frequency <= 350KHz
Parameter
Symbol
Unit
Min.
Max.
1.5
(2)
Min.
Max.
0.3VDD
(2)
Low level input voltage:
Fixed input levels
VIL
VIH
-0.5(1)
-0.5(1)
V
V
High level input voltage:
Fixed input levels
3.0
0.7VDD
Pulse width of spikes which must be
suppressed by the input filter
Capacitance for each I/O pin
tSP
Ci
n/a
-
n/a
10
50
-
50
10
ns
pF
Table 13: Two Wire Serial Interface - Characteristics of the SDA and SCL I/O Stages
Notes
(1): If Input voltage = < -0.3 Volts, then 20…100 Ohms resistor must be added in series
(2): Maximum VIH = VDDmax + 0.5 Volt
n/a: not applicable
SCL Clk frequency <= 100KHz
SCL Clk frequency <= 350KHz
Parameter
Symbol
Unit
Min.
Max.
Min.
Max.
SCL clock frequency
fSCL
0
100
0
350
KHz
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated.
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START
condition
tHD;STA
4.0
-
0.6
-
µs
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
µs
µs
tSU;STA
tSU;DAT
tr
4.7
250
-
-
-
0.6
100
-
-
µs
ns
ns
Data set-up time
Rise time of both SDA and SCL
signals
(1)
(1)
1000
20+0.1Cb
300
Fall time of both SDA and SCL
signals
tf
tSU;STO
tBUF
Cb
-
300
20+0.1Cb
300
ns
µs
µs
pF
Set-up time for STOP condition
Bus free time between a STOP
and START condition
4.0
4.7
0
-
-
0.6
1.3
-
-
-
Capacitive load for each bus line
Noise margin at the LOW level for
each connected device (including
hysteresis)
400
400
VnL
0.1VDD
0.2VDD
-
-
0.1VDD
0.2VDD
-
-
V
V
Noise margin at the HIGH level for
each connected device (including
hysteresis)
VnH
Table 14: Two Wire Serial Interface - Characteristics of the SDA and SCL bus lines
Notes
(1): Cb = total capacitance of one bus line in pF.
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