TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
22
TMC2041
TMC2041
#2
TMC2041
#3
NEXTADDR
NEXTADDR
CSN/IO0
NEXTADDR
CSN/IO0
#1
RFILT
RFILT
CFILT
CFILT
+VIO
+VIO
+VIO
1k
A
Master CPU
(µC with RS485
tranceiver)
RTERM
RTERM
B
EXAMPLE FOR ADDRESSING UP TO 255 TMC2041
Addressing phase 1:
Addressing phase 2:
Addressing phase 3:
Addressing phase 4:
Addressing phase X:
address 0, IO0 high
address 1
address 0, IO0 high
address 1
program to address 254 & set IO0 low
address 254
address 1
program to address 253 & set NAO low
address 253
address 0, IO0 high
address 254
program to address 252 & set IO0 low
continue procedure
Figure 5.2 Addressing multiple TMC2041 via differential interface, additional filtering for NEXTADDR
A different scheme (not shown) uses bus switches (like 74HC4066) to connect the bus to the next unit
in the chain without using the NAI input. The bus switch can be controlled in the same fashion, using
the NAO output to enable it (low level shall enable the bus switch). Once the bus switch is enabled it
allows addressing the next bus segment. As bus switches add a certain resistance, the maximum
number of nodes will be reduced.
It is possible to mix different styles of addressing in a system. For example a system using two
boards with each two TMC2041 can have both devices on a board with a different level on NEXTADDR,
while the next board is chained using analog switches separating the bus until the drivers on the first
board have been programmed.
www.trinamic.com
TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
