TSM931-TSM934
PACKAGE OUTLINE DRAWING
16-Pin SOIC Package Outline Drawing
(N.B., Drawings are not to scale)
10.01 Max
9.80 Min
( D)
1.27 TYP
0.79 Max
0.69 Min
0.508 REF
0.25
GAUGE PLANE
6.20 Max
3.99 Max
3.81 Min
5.80Min
7' TYP ALL SIDE
(E)
0' - 8'
0.863 Max
0.406 Min
DETAIL ‘A’
PIN 1
ID MARK
3.89 Max
3.73 Min
0.48 Max
0.28 Min
45' Angle
1.75 Max
3.99 Max
3.81 Min
0.25 Max
O.10 Min
0.25 Max
0.19 Min
0.51 Max
0.33 Min
0.10 Max
DETAIL ‘A’
NOTE:
1. “D” DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER SIDE.
2. “E” DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS.
INTER-LEAD FLASH AND PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.25 mm PER SIDE.
3. CONTROLLING DIMENSIONS IN MILIMETERS AND ANGLES IN DEGREES.
4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MS-012 AB
5. LEAD SPAN/STAND OFF HEIGHT/COPLANARITY ARE CONSIDERED AS SPECIAL CHARACTERISTIC.
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assume any responsibility for its use nor for any infringements of patents or other rights of third parties that may result from its use, and all
information provided by Touchstone Semiconductor and its suppliers is provided on an AS IS basis, WITHOUT WARRANTY OF ANY KIND.
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notice. No license is granted by implication or otherwise under any patent or patent rights of Touchstone Semiconductor. Touchstone
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applications using Touchstone Semiconductor components. To minimize the risk associated with customer products and applications,
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TSM931_34DS r1p0
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