TSM931-TSM934
PACKAGE OUTLINE DRAWING
8-Pin SOIC Package Outline Drawing
(N.B., Drawings are not to scale)
0.546 REF
0.33 - 0.51
5.80 – 6.20
1.27 TYP
2
3.73 - 3.89
0.48 Max
LEADFARME
THICKNESS
0.19 – 0.25
1
4.80 - 5.00
7' REF ALL SIDE
0.76 Max
0.66 Min
1.32 – 1.52
7' REF
0.28 Min
45' Angle
ALL SIDE
1.75 Max
GAUGE PLANE
0.25
3.81 – 3.99
2
0 - 8°
0.10 – 0.25
0.406 – 0.863
0.10 Max
Notes:
1
Does not include mold flash, protrusions or gate burns.
Mold flash, protrusions or gate burrs shall not exceed
0.15 mm per side.
Does not include inter-lead flash or protrusions. Inter-lead
flash or protrusions shall not exceed 0.25 mm per side.
2
Lead span/stand off height/coplanarity are considered as
special characteristic (s).
3.
4.
5.
6.
Controlling dimensions are in mm.
This part is compliant with JEDEC specification MS-012
Lead span/stand off height/coplanarity are considered as
Special characteristic.
Page 18
TSM931_34DS r1p0
RTFDS
TOUCHSTONE [ TOUCHSTONE SEMICONDUCTOR INC ]
