XC61F
Series
■Functional Description
GFunctional
Description ( CMOS output )
q
When a voltage higher than the release voltage (V
DR
) is applied to the voltage input pin (V
IN
), the voltage will gradually fall.
When a voltage higher than the detect voltage (V
DF
) is applied to V
IN
, output (V
OUT
) will be equal to the input at V
IN
.
Note that high impedeance exists at V
OUT
with the N-channel open drain configuration. If the pin is pulled up, V
OUT
will be
equal to the pull up voltage.
w
When V
IN
falls below V
DF
, V
OUT
will be equal to the ground voltage (V
SS
) level (detect state).
Note that this also applies to N-channel open drain configurations.
e
When V
IN
falls to a level below that of the minimum operating voltage (V
MIN
) output will become unstable.
Because the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up
voltage.
r
When V
IN
rises above the V
SS
level (excepting levels lower than minimum operating voltage), V
OUT
will be equal to V
SS
until
V
IN
reaches the V
DR
level.
t
Although V
IN
will rise to a level higher than V
DR
, V
OUT
maintains ground voltage level via the delay circuit.
y
Following transient delay time, V
IN
will be output at V
OUT
.
Note that high impedeance exists with the N-channel open drain configuration and that voltage will be dependent on pull up.
Notes :
1.
2.
The difference between V
DR
and V
DF
represents the hysteresis range.
Propagation delay time (tDLY) represents the time it takes for V
IN
to appear at V
OUT
once the said voltage has exceeded the
V
DR
level.
2
GTiming
Chart
■タイミングチャート
Input Voltage (V
IN
)
y
Detect Release Voltage (V
DR
)
Detect Voltage (V
DF
)
Minimum Operating Voltage
(
V
MIN
)
Ground Voltage (V
SS
)
Output Voltage (V
OUT
)
Propagation Delay Time (tDLY)
Ground Voltage (V
SS
)
q
w
e
r
t
y
163
TOREX [ TOREX SEMICONDUCTOR ]
