TTP259
TonTouchTM
Preliminary
P-4: 12-bit Timer/Counter/PWM for TCP2
One 12-bit timer/counter (TCP2) with 4 kind clock sources and preload
data buffer can implement as a timer or counter feature. The clock sources of
TCP2 are selected by TCP2S1~TCP2S0 of TCP2 control register (TCP2C).
TCP2OV is the timer or counter overflow signal and the rising edge will set the
relative INT flag.
TCP2C[203H]: TCP2 Timer/counter/PWM control register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TCP2LD
R/W
Bit2
TCP2S1
R/W
Bit1
TCP2S0
R/W
Bit0
TCP2EN
R/W
TCP2EN: TCP2 counting enable. (0: disable; 1: enable)
TCP2LD: TCP2 auto-reload enable. (0: disable; 1: enable)
TCP2S1~TCP2S0: TCP2 clock source selector.
TCP2S1
TCP2S0
Selected Clock source
0
0
1
1
0
1
0
1
FS
OSCH
TBCK
TCP1OV
TCP2L[204H]: TCP2 low nibble data register [R/W], default value [0000]
Register Bit3 Bit2 Bit1 Bit0
Bit Name TCP2_3/TCP2D3 TCP2_2/TCP2D2 TCP2_1/TCP2D1 TCP2_0/TCP2D0
Read/Write R/W R/W R/W R/W
TCP2_3~TCP2_0: Reading TCP2 counter low nibble data.
TCP2D3~TCP2D0: Writing TCP2D low nibble of data buffer.
TCP2M[205H]:TCP2 middle nibble data register [R/W], default value [0000]
Register
Bit Name TCP2_7/TCP2D7 TCP2_6/TCP2D6 TCP2_5/TCP2D5 TCP2_4/TCP2D4
Read/Write R/W R/W R/W R/W
Bit3
Bit2
Bit1
Bit0
TCP2_7~TCP2_4: Reading TCP2 counter middle nibble data.
TCP2D7~TCP2D4: Writing TCP2D middle nibble of data buffer.
2015/05/25
Page 33 of 81
Ver: 1.1
TTELEC [ TT Electronics ]
