ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢆ ꢀꢁꢁ ꢇ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢁ ꢇꢃ ꢄꢃ
ꢈꢉ ꢁꢊꢋ ꢌ ꢍꢋ ꢎ ꢏꢐ ꢑꢒꢁꢓꢋ ꢐ ꢍꢐ ꢏꢐꢏꢔ ꢀꢕ ꢒꢓꢋ ꢐ
ꢖ
SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009
APPLICATION INFORMATION
capacitor ripple reduction (continued)
UDG-97131
Figure 6. Timing Waveforms for Synchronization Scheme
Table 1. Effects of Synchronization on Boost Capacitor Current
V
IN
= 85 V
V
IN
= 120 V
V
IN
= 240 V
D(Q2)
0.35
Q1/Q2
D1/Q2
Q1/Q2
D1/Q2
Q1/Q2
D1/Q2
1.491 A
1.432 A
0.835 A
0.93 A
1.341 A
1.276 A
0.663 A
0.664 A
1.024 A
0.897 A
0.731 A
0.614 A
0.45
Table 1 illustrates that the boost capacitor ripple current can be reduced by about 50% at nominal line and about
30% at high line with the synchronization scheme facilitated by the UCC3817. Figure 7 shows the suggested
technique for synchronizing the UCC3817 to the downstream converter. With this technique, maximum ripple
reduction as shown in Figure 6 is achievable. The output capacitance value can be significantly reduced if its
choice is dictated by ripple current or the capacitor life can be increased as a result. In cost sensitive designs
where holdup time is not critical, this is a significant advantage.
An alternative method of synchronization to achieve the same ripple reduction is possible. In this method, the
turnon of Q1 is synchronized to the turnoff of Q2. While this method yields almost identical ripple reduction and
maintains trailing edge modulation on both converters, the synchronization is much more difficult to achieve and
the circuit can become susceptible to noise as the synchronizing edge itself is being modulated.
15
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